TM4C1233E6PZ Datasheet, PDF (1096/1242 Pages) Texas Instruments – Tiva Microcontroller

Universal Serial Bus (USB) Controller
area must be assigned to each endpoint. In the case of bulk, control and interrupt endpoints, each
has a maximum of 64 bytes per transaction. Isochronous endpoints can have packets with up to
1023 bytes per packet. In either mode, the maximum packet size for the given endpoint must be
set prior to sending or receiving data.
Configuring each endpoint's FIFO involves reserving a portion of the overall USB FIFO RAM to
each endpoint. The total FIFO RAM available is 2 Kbytes with the first 64 bytes reserved for endpoint
0. The endpoint's FIFO must be at least as large as the maximum packet size. The FIFO can also
be configured as a double-buffered FIFO so that interrupts occur at the end of each packet and
allow filling the other half of the FIFO.
The USB Device controller's soft connect must be enabled when the Device is ready to start
communications, indicating to the Host controller that the Device is ready to start the enumeration
process.
18.5
Register Map
Table 18-5 on page 1096 lists the registers. All addresses given are relative to the USB base address
of 0x4005.0000. Note that the USB controller clock must be enabled before the registers can be
programmed (see page 340). There must be a delay of 3 system clocks after the USB module clock
is enabled before any USB module registers are accessed.
Table 18-5. Universal Serial Bus (USB) Controller Register Map
Offset Name
Type
Reset
Description
0x000 USBFADDR
0x001 USBPOWER
0x002 USBTXIS
0x004 USBRXIS
0x006 USBTXIE
0x008 USBRXIE
0x00A USBIS
0x00B USBIE
0x00C USBFRAME
0x00E USBEPIDX
0x00F USBTEST
0x020 USBFIFO0
0x024 USBFIFO1
0x028 USBFIFO2
0x02C USBFIFO3
0x030 USBFIFO4
0x034 USBFIFO5
0x038 USBFIFO6
RW
0x00
USB Device Functional Address
RW
0x20
USB Power
RO
0x0000
USB Transmit Interrupt Status
RO
0x0000
USB Receive Interrupt Status
RW
0xFFFF
USB Transmit Interrupt Enable
RW
0xFFFE
USB Receive Interrupt Enable
RO
0x00
USB General Interrupt Status
RW
0x06
USB Interrupt Enable
RO
0x0000
USB Frame Value
RW
0x00
USB Endpoint Index
RW
0x00
USB Test Mode
RW
0x0000.0000 USB FIFO Endpoint 0
RW
0x0000.0000 USB FIFO Endpoint 1
RW
0x0000.0000 USB FIFO Endpoint 2
RW
0x0000.0000 USB FIFO Endpoint 3
RW
0x0000.0000 USB FIFO Endpoint 4
RW
0x0000.0000 USB FIFO Endpoint 5
RW
0x0000.0000 USB FIFO Endpoint 6
See
page
1100
1101
1103
1105
1106
1108
1109
1110
1111
1112
1113
1114
1114
1114
1114
1114
1114
1114
1096
Texas Instruments-Production Data
June 12, 2014