F28M36P63C2_15 Datasheet, PDF (109/253 Pages) Texas Instruments – Concerto Microcontrollers

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F28M36P63C2, F28M36P53C2, F28M36H53C2, F28M36H53B2
F28M36H33C2, F28M36H33B2
SPRS825D – OCTOBER 2012 – REVISED OCTOBER 2015
5.11.1.2 Transmit FIFO
The transmit FIFO is a 16-bit-wide, 8-location-deep, first-in, first-out memory buffer. The CPU writes data to the
FIFO through the SSI Data (SSIDR) register, and data is stored in the FIFO until the data is read out by the
transmission logic. When configured as a master or a slave, parallel data is written into the transmit FIFO before
serial conversion and transmission to the attached slave or master, respectively, through the SSITx pin.
In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit FIFO is empty
and the master initiates a transaction, the slave transmits the 8th most recent value in the transmit FIFO. If less
than eight values have been written to the transmit FIFO since the SSI module clock was enabled using the SSI
bit in the RGCG1 register, then "0" is transmitted. Care should be taken to ensure that valid data is in the FIFO
as needed. The SSI can be configured to generate an interrupt or an µDMA request when the FIFO is empty.
5.11.1.3 Receive FIFO
The receive FIFO is a 16-bit-wide, 8-location-deep, first-in, first-out memory buffer. Received data from the serial
interface is stored in the buffer until read out by the CPU, which accesses the read FIFO by reading the SSIDR
register. When configured as a master or slave, serial data received through the SSIRx pin is registered before
parallel loading into the attached slave or master receive FIFO, respectively.
5.11.1.4 Interrupts
The SSI can generate interrupts when the following conditions are observed:
• Transmit FIFO service (when the transmit FIFO is half full or less)
• Receive FIFO service (when the receive FIFO is half full or more)
• Receive FIFO time-out
• Receive FIFO overrun
• End of transmission
All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI generates a
single interrupt request to the controller regardless of the number of active interrupts. Each of the four individual
maskable interrupts can be masked by clearing the appropriate bit in the SSI Interrupt Mask (SSIIM) register.
Setting the appropriate mask bit enables the interrupt.
The individual outputs, along with a combined interrupt output, allow the use of either a global interrupt service
routine or modular device drivers to handle interrupts. The transmit and receive dynamic data-flow interrupts
have been separated from the status interrupts so that data can be read or written in response to the FIFO
trigger levels. The status of the individual interrupt sources can be read from the SSI Raw Interrupt Status
(SSIRIS) and SSI Masked Interrupt Status (SSIMIS) registers.
The receive FIFO has a time-out period that is 32 periods at the rate of SSIClk (whether or not SSIClk is
currently active) and is started when the RX FIFO goes from EMPTY to not-EMPTY. If the RX FIFO is emptied
before 32 clocks have passed, the time-out period is reset. As a result, the ISR should clear the Receive FIFO
Time-out Interrupt just after reading out the RX FIFO by writing a "1" to the RTIC bit in the SSI Interrupt Clear
(SSIICR) register. The interrupt should not be cleared so late that the ISR returns before the interrupt is actually
cleared, or the ISR may be reactivated unnecessarily.
The End-of-Transmission (EOT) interrupt indicates that the data has been transmitted completely. This interrupt
can be used to indicate when it is safe to turn off the SSI module clock or enter sleep mode. In addition, because
transmitted data and received data complete at exactly the same time, the interrupt can also indicate that read
data is ready immediately, without waiting for the receive FIFO time-out period to complete.
Copyright © 2012–2015, Texas Instruments Incorporated
Specifications 109
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