F28M36P63C2_15 Datasheet, PDF (1/253 Pages) Texas Instruments – Concerto Microcontrollers

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F28M36P63C2, F28M36P53C2, F28M36H53C2, F28M36H53B2
F28M36H33C2, F28M36H33B2
SPRS825D – OCTOBER 2012 – REVISED OCTOBER 2015
F28M36x Concerto™ Microcontrollers
1 Device Overview
1.1 Features
1
• Master Subsystem — ARM^® Cortex^®-M3
– 125 MHz
– Embedded Memory
• Up to 1MB of Flash (ECC)
• Up to 128KB of RAM (ECC or Parity)
• Up to 64KB of Shared RAM
• 2KB of IPC Message RAM
– Five Universal Asynchronous
Receiver/Transmitters (UARTs)
– Four Synchronous Serial Interfaces (SSIs)
and a Serial Peripheral Interface (SPI)
– Two Inter-integrated Circuits (I²Cs)
– Universal Serial Bus On-the-Go (USB-OTG) +
PHY
– 10/100 ENET 1588 MII
– Two Controller Area Network, D_CAN, Modules
(Pin-Bootable)
– 32-Channel Micro Direct Memory Access
(µDMA)
– Dual Security Zones (128-Bit Password per
Zone)
– External Peripheral Interface (EPI)
– Micro Cyclic Redundancy Check (µCRC)
Module
– Four General-Purpose Timers
– Two Watchdog Timer Modules
– Endianness: Little Endian
• Clocking
– On-chip Crystal Oscillator and External Clock
Input
– Dynamic Phase-Locked Loop (PLL) Ratio
Changes Supported
• 1.2-V Digital, 1.8-V Analog, 3.3-V I/O Design
• Interprocessor Communications (IPC)
– 32 Handshaking Channels
– Four Channels Generate IPC Interrupts
– Can be Used to Coordinate Transfer of Data
Through IPC Message RAMs
• Up to 142 Individually Programmable, Multiplexed
General-Purpose Input/Output (GPIO) Pins
– Glitch-free I/Os
• Control Subsystem — TMS320C28x 32-Bit CPU
– 150 MHz
– C28x Core Hardware Built-in Self-Test
– Embedded Memory
• Up to 512KB of Flash (ECC)
• Up to 36KB of RAM (ECC or Parity)
• Up to 64KB of Shared RAM
• 2KB of IPC Message RAM
– IEEE-754 Single-Precision Floating-Point Unit
(FPU)
– Viterbi, Complex Math, CRC Unit (VCU)
– Serial Communications Interface (SCI)
– SPI
– I²C
– 6-Channel Direct Memory Access (DMA)
– 12 Enhanced Pulse Width Modulator (ePWM)
Modules
• 24 Outputs (16 High-Resolution)
– Six 32-Bit Enhanced Capture (eCAP) Modules
– Three 32-Bit Enhanced Quadrature Encoder
Pulse (eQEP) Modules
– Multichannel Buffered Serial Port (McBSP)
– EPI
– One Security Zone (128-Bit Password)
– Three 32-Bit Timers
– Endianness: Little Endian
• Analog Subsystem
– Dual 12-Bit Analog-to-Digital Converters (ADCs)
– Up to 2.88 MSPS
– Up to 24 Channels
– Four Sample-and-Hold (S/H) Circuits
– Up to Six Comparators With 10-Bit Digital-to-
Analog Converter (DAC)
• Package
– 289-Ball ZWT New Fine Pitch Ball Grid Array
(nFBGA)
• Temperature Options:
– T: –40ºC to 105ºC Junction
– S: –40ºC to 125ºC Junction
– Q: –40ºC to 125ºC Free-Air
(Q100 Qualification for Automotive Applications)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.