LM3S9790_15 Datasheet, PDF (1083/1306 Pages) Texas Instruments – Stellaris LM3S9790 Microcontroller

Stellaris^® LM3S9790 Microcontroller
Bit/Field
6
5
4
3
2
1:0
Name
ISO
MODE
DMAEN
FDT
DMAMOD
reserved
Type
R/W
R/W
R/W
R/W
R/W
RO
Reset
0
Description
Isochronous Transfers
Value Description
0 Enables the transmit endpoint for bulk or interrupt transfers.
1 Enables the transmit endpoint for isochronous transfers.
0
Mode
Value Description
0 Enables the endpoint direction as RX.
1 Enables the endpoint direction as TX.
Note: This bit only has an effect where the same endpoint FIFO is
used for both transmit and receive transactions.
0
DMA Request Enable
Value Description
0 Disables the µDMA request for the transmit endpoint.
1 Enables the µDMA request for the transmit endpoint.
Note:
3 TX and 3 RX endpoints can be connected to the µDMA
module. If this bit is set for a particular endpoint, the DMAATX,
DMABTX, or DMACTX field in the USB DMA Select
(USBDMASEL) register must be programmed
correspondingly.
0
Force Data Toggle
Value Description
0 No effect.
1 Forces the endpoint DT bit to switch and the data packet to be
cleared from the FIFO, regardless of whether an ACK was
received. This bit can be used by interrupt transmit endpoints
that are used to communicate rate feedback for isochronous
endpoints.
0
DMA Request Mode
Value Description
0 An interrupt is generated after every µDMA packet transfer.
1 An interrupt is generated only after the entire μDMA transfer is
complete.
Note: This bit must not be cleared either before or in the same cycle
as the above DMAEN bit is cleared.
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
July 03, 2014
Texas Instruments-Production Data
1083