LMK04208 Datasheet, PDF (106/138 Pages) Texas Instruments – Low-Noise Clock Jitter Cleaner with Dual Loop PLLs

LMK04208
SNAS684 – SEPTEMBER 2016
www.ti.com
9.1.7 Calculating Dynamic Digital Delay Values for Any Divide
This section explains how to calculate the dynamic digital delay for any divide value.
Dynamic digital delay allows the time offset between two or more clock outputs to be adjusted with no or minimal
interruption of clock outputs. Since the clock outputs are operating at a known frequency, the time offset can also
be expressed as a phase shift. When dynamically adjusting the digital delay of clock outputs with different
frequencies the phase shift should be expressed in terms of the higher frequency clock. The step size of the
smallest time adjustment possible is equal to half the period of the Clock Distribution Path, which is the VCO
frequency (Equation 3) or the VCO frequency divided by the VCO divider (Equation 4) if not bypassed. The
smallest degree phase adjustment with respect to a clock frequency will be 360 * the smallest time adjustment *
the clock frequency. The total number of phase offsets that the LMK04208 is able to achieve using dynamic
digital delay is equal 1 / (higher clock frequency * the smallest phase adjustment).
Equation 7 calculates the digital delay value that must be programmed for a synchronizing clock to achieve a 0
time/phase offset from the qualifying clock. Once this digital delay value is known, it is possible to calculate the
digital delay value for any phase offset. The qualifying clock for dynamic digital delay is selected by the
FEEDBACK_MUX. When dynamic digital delay is engaged with same clock output used for the qualifying clock
and the new synchronized clock, it is termed relative dynamic digital delay since causing another SYNC event
with the same digital delay value will offset the clock by the same phase once again. The important part of
relative dynamic digital delay is that the CLKoutX_HS must be programmed correctly when the SYNC event
occurs (Table 6). This can result in needing to program the device twice. Once to set the new CLKoutX_DDLY
with CLKoutX_HS as required for the SYNC event, and again to set the CLKoutX_HS to its desired value.
Digital delay values are programmed using the CLKoutX_DDLY and CLKoutX_HS registers as shown in
Equation 8. For example, to achieve a digital delay of 13.5, program CLKoutX_DDLY = 14 and CLKoutX_HS = 1.
0
digital
delay
=
¨§
©
¨§
©
ª
16
º
««CLKoutX_Y_DIV»»
+
0.5¸¹·
u
CLKoutX_Y_DIV¸·
¹
-
11.5
(7)
Equation 7 uses the ceiling operator. To find the ceiling of a fractional number round up. An integer remains the
same value.
Digital delay = CLKoutX_DDLY - (0.5 * CLKoutX_HS)
(8)
Note: since the digital delay value for 0 time/phase offset is a function of the qualifying clock's divide value, the
resulting digital delay value can be used for any clock output operating at any frequency to achieve a 0
time/phase offset from the qualifying clock. Therefore the calculated time shift table will also be the same as in
Table 115.
9.1.7.1 Example
Consider a system with:
• A VCO frequency of 3000 MHz.
• The VCO divider is bypassed, therefore the clock distribution path frequency is 3000 MHz.
• CLKout0_DIV = 10 resulting in a 300 MHz frequency on CLKout0.
• CLKout1_DIV = 20 resulting in a 150 MHz frequency on CLKout2.
For this system the minimum time adjustment is ~0.16667 ns, which is 0.5 / (3000 MHz). Since the higher
frequency is 300 MHz, phase adjustments will be calculated with respect to the 300 MHz frequency. The 0.25 ns
minimum time adjustment results in a minimum phase adjustment of 18 degrees, which is 360 degrees / 200
MHz * 0.25 ns.
To calculate the digital delay value to achieve a 0 time/phase shift of CLKout2 when CLKout0 is the qualifying
clock. Solve Equation 7 using the divide value of 10. To solve the equation 16/10 = 1.6, the ceiling of 1.6 is 2.
Then to finish solving the equation solve (2 + 0.5) * 10 - 11.5 = 13.5. A digital delay value of 13.5 is programmed
by setting CLKout1_DDLY = 14 and CLKout1_HS = 1.
To calculate the digital delay value to achieve a 0 time/phase shift of CLKout0 when CLKout2 is the qualifying
clock, solve Equation 7 using the divide value of CLKout2, which is 20. This results in a digital delay of 18.5
which is programmed as CLKout0_DDLY = 19 and CLKout0_HS = 1.
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