LMK04208 Datasheet, PDF (1/138 Pages) Texas Instruments – Low-Noise Clock Jitter Cleaner with Dual Loop PLLs

Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
LMK04208
SNAS684 – SEPTEMBER 2016
LMK04208 Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
1 Features
•1 Ultra-Low RMS Jitter Performance
– 111 fs, RMS Jitter (12 kHz to 20 MHz)
– 123 fs, RMS Jitter (100 Hz to 20 MHz)
• Dual Loop PLLatinum™ PLL Architecture
• PLL1
– Integrated Low-Noise Crystal Oscillator Circuit
– Holdover Mode when Input Clocks are Lost
– Automatic or Manual Triggering/Recovery
• PLL2
– Normalized PLL Noise Floor of –227 dBc/Hz
– Phase Detector Rate of Up to 155 MHz
– OSCin Frequency-Doubler
– Integrated Low-Noise VCO or External VCO
Mode
• Two Redundant Input Clocks with LOS
– Automatic and Manual Switch-Over Modes
• 50 % Duty Cycle Output Divides, 1 to 1045 (Even
and Odd)
• 6 LVPECL, LVDS, or LVCMOS Programmable
Outputs
• Digital Delay: Fixed or Dynamically Adjustable
• 25 ps Step Analog Delay Control
• 7 Differential Outputs, Up to 14 Single-Ended
– Up to 6 VCXO/Crystal Buffered Outputs
• Clock Rates of Up to 1536 MHz
• 0-Delay Mode
• Three Default Clock Outputs at Power Up
• Multi-Mode: Dual PLL, Single PLL, and Clock
Distribution
• Industrial Temperature Range: –40°C to +85°C
• 3.15-V to 3.45-V Operation
• 64-Pin WQFN Package (9.0 × 9.0 × 0.8 mm)
2 Applications
• Data Converter Clocking
• Wireless Infrastructure
• Networking, SONET/SDH, DSLAM
• Medical, Video, Military, Aerospace
• Test and Measurement
3 Description
The LMK04208 is a high performance clock
conditioner with superior clock jitter cleaning,
generation, and distribution with advanced features to
meet next generation system requirements. The dual
loop PLLatinum™ architecture is capable of 111 fs,
RMS jitter (12 kHz to 20 MHz) using a low-noise
VCXO module or sub-200 fs rms jitter (12 kHz to 20
MHz) using a low cost external crystal and varactor
diode.
The dual loop architecture consists of two high-
performance phase-locked loops (PLL), a low-noise
crystal oscillator circuit, and a high-performance
voltage controlled oscillator (VCO). The first PLL
(PLL1) provides low-noise jitter cleaner functionality
while the second PLL (PLL2) performs the clock
generation. PLL1 can be configured to either work
with an external VCXO module or the integrated
crystal oscillator with an external tunable crystal and
varactor diode. When paired with a very narrow loop
bandwidth, PLL1 uses the superior close-in phase
noise (offsets below 50 kHz) of the VCXO module or
the tunable crystal to clean the input clock. The
output of PLL1 is used as the clean input reference to
PLL2 where it locks the integrated VCO. The loop
bandwidth of PLL2 can be optimized to clean the far-
out phase noise (offsets above 50 kHz) where the
integrated VCO outperforms the VCXO module or
tunable crystal used in PLL1.
Device Information⁽¹⁾
PART NUMBER
VCO FREQUENCY
LMK04208
2750 to 3072 MHz
CLOCK
INPUTS
2
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
Crystal or
VCXO
OSCout
Recovered
³GLUW\´ FORFNV
or clean clocks _CLKin0
CLKin1
Backup
Reference
Clock
LMK04208
Precision Clock
Conditioner
CLKout0
CLKout1
CLKout2
CLKout3
CLKout4
CLKout5
LMX2582
PLL+VCO
Serializer/
Deserializer
ADC _DAC
FPGA
CPLD
0XOWLSOH ³FOHDQ´ FORFNV DW GLIIHUHQW
frequencies
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.