TMS320C6711D_15 Datasheet, PDF (100/109 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSOR

TMS320C6711D
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS292B − OCTOBER 2005 − REVISED JUNE 2006
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1^†‡ (see Figure 51)
GDPA−167
ZDPA−167
−200
NO.
−250
MASTER
SLAVE
MIN MAX
MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high
5 th(CKXH-DRV) Hold time, DR valid after CLKX high
12
2 − 6P
4
5 + 12P
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.}
‡ _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
UNIT
ns
ns
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 11b, CLKXP = 1^†‡ (see Figure 51)
NO.
PARAMETER
1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶
2 td(FXL-CKXL) Delay time, FSX low to CLKX low#
3 td(CKXH-DXV) Delay time, CLKX high to DX valid
Disable time, DX high impedance following last data bit from
6 tdis(CKXH-DXHZ) _{CLKX high}
GDPA−167
ZDPA−167
−200
−250
MASTER§
SLAVE
MIN MAX
MIN
MAX
H−2 H+3
T−2 T+3
−3
4 6P + 2 10P + 17
UNIT
ns
ns
ns
−2
4 6P + 3 10P + 17 ns
7 td(FXL-DXV)
Delay time, FSX low to DX valid
L − 2 L + 6.5 4P + 2 8P + 17 ns
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.}
‡ _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
§ _{S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)}
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶ _{FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX}
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# _{FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock}
(CLKX).
CLKX
1
FSX
6
DX
Bit 0
DR
Bit 0
2
7
Bit(n-1)
4
Bit(n-1)
3
(n-2)
5
(n-2)
(n-3)
(n-4)
(n-3)
(n-4)
Figure 51. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
100
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