TM248NBK36E Datasheet, PDF (10/12 Pages) Texas Instruments – 36-BIT DYNAMIC RAM MODULE

TM124MBK36E, TM124MBK36T 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBK36E, TM248NBK36T 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS139 – MARCH 1994
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’124MBK36E - 60 ’124MBK36E - 70 ’124MBK36E - 80
’248NBK36E - 60 ’248NBK36E - 70 ’248NBK36E - 80
MIN MAX MIN MAX MIN MAX
tCAH Hold time, column address after CAS low
10
15
15
tDHR Hold time, data after RAS low (see Note 10)
50
55
60
tDH
Hold time, data
10
15
15
tAR
Hold time, column address after RAS low (see Note 10)
50
55
60
tCLCH Hold time, CAS low to CAS high
5
5
5
tRAH Hold time, row address after RAS low
10
10
10
tRCH Hold time, read after CAS high (see Note 11)
0
0
0
tRRH Hold time, read after RAS high (see Note 11)
0
0
0
tWCH Hold time, write after CAS low
15
15
15
tWCR Hold time, write after RAS low (see Note 10)
50
55
60
tWHR Hold time, W high (see Note 9)
10
10
10
tCHR Delay time, RAS low to CAS high (see Note 9)
15
15
20
tCRP Delay time, CAS high to RAS low
0
0
0
tCSH Delay time, RAS low to CAS high
60
70
80
tCSR Delay time, CAS low to RAS low (see Note 9)
10
10
10
tRAD Delay time, RAS low to column address (see Note 12)
15
30
15
35
15
40
tRAL Delay time, column address to RAS high
30
35
40
tCAL Delay time, column address to CAS high
30
35
40
tRCD Delay time, RAS low to CAS low (see Note 12)
20
45
20
52
20
60
tRPC Delay time, RAS high to CAS low (see Note 9)
0
0
0
tRSH Delay time, CAS low to RAS high
15
18
20
tREF Refresh time interval
16
16
16
tT
Transition time
2
50
2
50
2
50
NOTES: 9. CAS-before-RAS refresh only
10. The minimum value is measured when tRCD is set to tRCD min as a reference.
11. Either tRRH or tRCH must be satisfied for a read cycle.
12. The maximum value is specified only to assure access time.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
10
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443