TCA6408A Datasheet, PDF (10/35 Pages) Texas Instruments – LOW-VOLTAGE 8-BIT I2C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

TCA6408A
SCPS192C – APRIL 2009– REVISED JULY 2009............................................................................................................................................................. www.ti.com
Interrupt (INT)Output
An interrupt is generated by a rising or falling edge of the port inputs in the input mode. After time t_iv, the signal
INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or
when data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur
during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this
pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the
state of the pin does not match the contents of the Input Port Register.
The INT output has an open-drain structure and requires a pullup resistor to V_CCP or V_CCI depending on the
application. INT should be connected to the voltage source of the device that requires the interrupt information.
Bus Transactions
Data is exchanged between the master and TCA6408A through write and read commands.
Writes
Data is transmitted to the TCA6408A by sending the device address and setting the least significant bit (LSB) to
a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which
register receives the data that follows the command byte. There is no limitation on the number of data bytes sent
in one write transmission.
SCL
12 3456 78 9
Slave Address
Command Byte
Data to Port
SDA
S0 1 0
00
0
AD
DR
0
A
0
00
00
00
1A
Data 1
AP
Start Condition
R/W ACK From Slave
ACK From Slave
ACK From Slave
Write to Port
Data Out
From Port
Figure 6. Write to Output Port Register
Data 1 Valid
t_pv
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SCL 1 2 3 4 5 6 7 8 9
Slave Address
Command Byte
Data to Register
SDA
S
010
00
0
AD
DR
0
A
0
00
00
0 1 1/0 A
Data
Start Condition
R/W ACK From Slave
ACK From Slave
Figure 7. Write to Configuration or Polarity Inversion Registers
AP
ACK From Slave
10
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