SN74GTLPH1616 Datasheet, PDF (10/18 Pages) Texas Instruments – 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS

SN74GTLPH1616
17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
SCES346C – JANUARY 2001 – REVISED DECEMBER 2005
www.ti.com
Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature,
V_TT = 1.5 V and V_REF = 1 V for GTLP (normal mode) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE⁽¹⁾
f_max
t_PLH
A
t_PHL
B
Slow
t_PLH
A
t_PHL
B
Fast
t_PLH
LEAB
B
t_PHL
Slow
t_PLH
LEAB
B
t_PHL
Fast
t_PLH
CLKAB
B
t_PHL
Slow
t_PLH
CLKAB
B
t_PHL
Fast
t_PLH
CLKAB
CLKOUT
Slow
t_PHL
t_PLH
CLKAB
CLKOUT
Fast
t_PHL
t_en
OEAB
B or CLKOUT
Slow
t_dis
t_en
OEAB
B or CLKOUT
Fast
t_dis
Slow
t_r
Rise time, B outputs (20% to 80%)
Fast
Slow
t_f
Fall time, B outputs (80% to 20%)
Fast
t_PLH
B
A
—
t_PHL
t_PLH
LEBA
A
—
t_PHL
t_PLH
CLKBA
A
—
t_PHL
t_PLH
CLKOUT
CLKIN
—
t_PHL
t_en
OEBA
A or CLKIN
—
t_dis
MIN TYP⁽²⁾ MAX UNIT
175
MHz
4.3 5.6 7.1
ns
3.2 4.6 6.4
3.2 4.3 5.6
ns
2.7 3.9 5.3
4.8 6.2 7.8
ns
3.5 4.9 6.7
3.5 4.8 6.2
ns
3.1 4.3 5.8
4.8 6.1 7.6
ns
3.5 4.8 6.6
3.6 4.9 6.2
ns
3.1 4.3 5.7
5.5 6.9 8.5
ns
5.5
7 9.3
4 5.3 6.7
ns
4.4 5.8 7.6
4.8 6.2 7.8
ns
3.4 5.2 7.8
3.6 4.8 6.2
ns
3 4.4 6.1
2.5
ns
1.4
3.3
ns
2.4
1.1 2.8 4.3
ns
1.9 3.1 4.1
1.3 3.1 4.6
ns
1.4 2.6 3.8
1.3 3.3 4.8
ns
1.8 2.9 4.1
2.2 3.7 5.3
ns
2.7 3.9 5.1
1.2 2.9 4.8
ns
2.3
4 5.5
(1) Slow (ERC = GND) and Fast (ERC = V_CC)
(2) All typical values are at V_CC = 3.3 V, T_A = 25°C.
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