SN74GTLPH1616 Datasheet, PDF (1/18 Pages) Texas Instruments – 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS

SN74GTLPH1616
17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
www.ti.com
SCES346C – JANUARY 2001 – REVISED DECEMBER 2005
FEATURES
• Member of the Texas Instruments Widebus™
Family
• UBT™ Transceiver Combines D-Type Latches
and D-Type Flip-Flops for Operation in
Transparent, Latched, Clocked, or
Clock-Enabled Modes
• TI-OPC™ Circuitry Limits Ringing on
Unevenly Loaded Backplanes
• OEC™ Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
• Bidirectional Interface Between GTLP Signal
Levels and LVTTL Logic Levels
• GTLP Buffered CLKAB Signal (CLKOUT)
• LVTTL Interfaces Are 5-V Tolerant
• High-Drive GTLP Outputs (100 mA)
• LVTTL Outputs (–24 mA/24 mA)
• Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for Optimal
Data-Transfer Rate and Signal Integrity in
Distributed Loads
• I_off, Power-Up 3-State, and BIAS V_CC Support
Live Insertion
• Bus Hold on A-Port Data Inputs
• Distributed V_CC and GND Pins Minimize
High-Speed Switching Noise
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DGG PACKAGE
(TOP VIEW)
OEAB 1
LEAB 2
A1 3
A2 4
GND 5
A3 6
V_CC 7
A4 8
A5 9
GND 10
A6 11
A7 12
A8 13
GND 14
A9 15
V_CC 16
A10 17
GND 18
A11 19
A12 20
GND 21
A13 22
A14 23
GND 24
A15 25
V_CC 26
A16 27
ERC 28
A17 29
CLKIN 30
OEBA 31
LEBA 32
64 CEAB
63 CLKAB
62 B1
61 B2
60 GND
59 B3
58 BIAS V_CC
57 B4
56 B5
55 GND
54 B6
53 B7
52 B8
51 GND
50 B9
49 V_CC
48 B10
47 GND
46 B11
45 B12
44 GND
43 B13
42 B14
41 GND
40 B15
39 V_REF
38 B16
37 GND
36 B17
35 CLKOUT
34 CLKBA
33 CEBA
DESCRIPTION/ORDERING INFORMATION
The SN74GTLPH1616 is a high-drive, 17-bit UBT™ transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. The device allows for transparent, latched, clocked, or clock-enabled
modes of data transfer. Additionally, it provides for a copy of CLKAB at GTLP signal levels (CLKOUT) and
conversion of a GTLP clock to LVTTL logic levels (CLKIN). The device provides a high-speed interface between
cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three
times faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP's reduced output swing
(<1 V), reduced input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry.
Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using
several backplane models. The high drive allows incident-wave switching in heavily loaded backplanes, with
equivalent load impedance down to 11 Ω.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, UBT, TI-OPC, OEC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2005, Texas Instruments Incorporated