MSP430F23X0 Datasheet, PDF (10/67 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430F23x0
SLAS518E – AUGUST 2006 – REVISED AUGUST 2011
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Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range of 0xFFFF to 0xFFC0.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0xFFFE) contains 0xFFFF (for example, if flash is not programmed), the
CPU goes into LPM4 immediately after power up.
Table 6. Interrupt Vector Addresses
INTERRUPT SOURCE
Power-up
External Reset
Watchdog
Flash key violation
PC out of range⁽¹⁾
NMI
Oscillator Fault
Flash memory access violation
Timer_B3
Timer_B3
Comparator_A+
Watchdog timer
Timer_A3
Timer_A3
USCI_A0/USCI_B0 Receive
USCI_B0 I2C Status
USCI_A0/USCI_B0 Transmit
USCI_B0 I2C Receive/Transmit
INTERRUPT FLAG
PORIFG
RSTIFG
WDTIFG
KEYV
(2)
NMIIFG
OFIFG
ACCVIFG ^{(2) (3)}
TBCCR0 CCIFG⁽⁴⁾
TBCCR1 and TBCCR2,
CCIFGs, TBIFG⁽²⁾⁽⁴⁾
CAIFG
WDTIFG
TACCR0 CCIFG⁽⁴⁾
TACCR1 CCIFG,
TACCR2 CCIFG,
TAIFG^{(2) (4)}
UCA0RXIFG,
UCB0RXIFG ^{(2) (5)}
UCA0TXIFG,
UCB0TXIFG ^{(2) (6)}
SYSTEM
INTERRUPT
Reset
(non)–maskable
(non)–maskable
(non)–maskable
maskable
maskable
maskable
maskable
maskable
maskable
maskable
maskable
I/O port P2 (eight flags)
I/O port P1 (eight flags)
P2IFG.0 to P2IFG.7⁽²⁾⁽³⁾
P1IFG.0 to P1IFG.7⁽²⁾⁽³⁾
maskable
maskable
See ⁽⁷⁾
See ⁽⁸⁾
WORD ADDRESS
0xFFFE
0xFFFC
0xFFFA
0xFFF8
0xFFF6
0xFFF4
0xFFF2
0xFFF0
0xFFEE
0xFFEC
0xFFEA
0xFFE8
0xFFE6
0xFFE4
0xFFE2
0xFFE0
0xFFDE
0xFFDC to 0xFFC0
PRIORITY
31, highest
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14 to 0, lowest
(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0x0000 to 0x01FF) or
from within unused address range.
(2) Multiple source flags
(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.
(4) Interrupt flags are located in the module.
(5) In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG
(6) In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG
(7) This location is used as bootstrap loader security key (BSLSKEY).
A 0xAA55 at this location disables the BSL completely.
A zero (0x0) disables the erasure of the flash if an invalid password is supplied.
(8) The interrupt vectors at addresses 0xFFDC to 0xFFC0 are not used in this device and can be used for regular program code if
necessary.
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