LP38859_14 Datasheet, PDF (10/21 Pages) Texas Instruments – 3A Fast-Response High-Accuracy LDO Linear Regulator with Soft-Start

LP38859
SNVS337D – JUNE 2006 – REVISED OCTOBER 2011
www.ti.com
Aluminum electrolytic capacitors can be used, but are not recommended as their ESR increases very quickly at
cold temperatures. They are not recommended for any application where the ambient temperature falls below
0°C.
Bias Capacitor
The capacitor on the bias pin must be at least 1 µF, and can be any good quality capacitor (ceramic is
recommended).
INPUT VOLTAGE
The input voltage (V_IN) is the high current external voltage rail that will be regulated down to a lower voltage,
which is applied to the load. The input voltage must be at least V_OUT + V_DO, and no higher than whatever values
is used for V_BIAS.
BIAS VOLTAGE
The bias voltage (V_BIAS) is a low current external voltage rail required to bias the control circuitry and provide
gate drive for the N-FET pass transistor. The bias voltage must be in the range of 3.0V to 5.5V to ensure proper
operation of the device.
UNDER VOLTAGE LOCKOUT
The bias voltage is monitored by a circuit which prevents the device from functioning when the bias voltage is
below the Under-Voltage Lock-Out (UVLO) threshold of approximately 2.45V.
As the bias voltage rises above the UVLO threshold the device control circuitry becomes active. There is
approximately 150 mV of hysteresis built into the UVLO threshold to provide noise immunity.
When the bias voltage is between the UVLO threshold and the Minimum Operating Rating value of 3.0V the
device will be functional, but the operating parameters will not be within the specified limits.
SUPPLY SEQUENCING
There is no requirement for the order that V_IN or V_BIAS are applied or removed.
One practical limitation is that the Soft-Start circuit starts charging C_SS when V_BIAS rises above the UVLO
threshold. If the application of V_IN is delayed beyond this point the benefits of Soft-Start will be compromised.
In any case, the output voltage cannot be specified until both V_IN and V_BIAS are within the range of specified
operating values.
If used in a dual-supply system where the regulator output load is returned to a negative supply, the output pin
must be diode clamped to ground. A Schottky diode is recommended for this diode clamp.
REVERSE VOLTAGE
A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin.
Typically this will happen when V_IN is abruptly taken low and C_OUT continues to hold a sufficient charge such that
the input to output voltage becomes reversed.
The NMOS pass element, by design, contains no body diode. This means that, as long as the gate of the pass
element is not driven, there will not be any reverse current flow through the pass element during a reverse
voltage event. The gate of the pass element is not driven when V_BIAS is below the UVLO threshold.
When V_BIAS is above the UVLO threshold the control circuitry is active and will attempt to regulate the output
voltage. Since the input voltage is less than the output voltage the control circuit will drive the gate of the pass
element to the full V_BIAS potential when the output voltage begins to fall. In this condition, reverse current will flow
from the output pin to the input pin , limited only by the R_DS(ON) of the pass element and the output to input
voltage differential. This condition is outside the specified operating range and should be avoided.
10
Submit Documentation Feedback
Product Folder Links: LP38859
Copyright © 2006–2011, Texas Instruments Incorporated