LMH6702QML Datasheet, PDF (10/14 Pages) Texas Instruments – 1.7 GHz, Ultra Low Distortion, Wideband Op Amp

20151629
FIGURE 4. Input Amplifier to ADC
The series resistor, R_S, between the amplifier output and the
ADC input is critical to achieving best system performance.
This load capacitance, if applied directly to the output pin, can
quickly lead to unacceptable levels of ringing in the pulse re-
sponse. The plot of "R_S and Settling Time vs. C_L" in the
Typical Performance Characteristics section is an excellent
starting point for selecting R_S. The value derived in that plot
minimizes the step settling time into a fixed discrete capacitive
load with the output driving a very light resistive load (1kΩ).
Sensitivity to capacitive loading is greatly reduced once the
output is loaded more heavily. Therefore, for cases where the
output is heavily loaded, R_S value may be reduced. The exact
value may best be determined experimentally for these cas-
es.
In applications where the LMH6702 is replacing the CLC409,
care must be taken when the device is lightly loaded and
some capacitance is present at the output. Due to the much
higher frequency response of the LMH6702 compared to the
CLC409, there could be increased susceptibility to low value
output capacitance (parasitic or inherent to the board layout
or otherwise being part of the output load). As already men-
tioned, this susceptibility is most noticeable when the
LMH6702's resistive load is light. Parasitic capacitance can
be minimized by careful lay out. Addition of an output snubber
R-C network will also help by increasing the high frequency
resistive loading.
Referring back to Figure 4, it must be noted that several ad-
ditional constraints should be considered in driving the ca-
pacitive input of an ADC. There is an option to increase R_S,
band-limiting at the ADC input for either noise or Nyquist
Device
Package
Evaluation Board
Part Number
LMH6702QMLMF SOT23-5
CLC730216
LMH6702QMLMA Plastic SOIC
CLC730227
band-limiting purposes. Increasing R_S too much, however,
can induce an unacceptably large input glitch due to switching
transients coupling through from the "convert" signal. Also,
C_IN is oftentimes a voltage dependent capacitance. This input
impedance non-linearity will induce distortion terms that will
increase as R_S is increased. Only slight adjustments up or
down from the recommended R_S value should therefore be
attempted in optimizing system performance.
DC ACCURACY AND NOISE
Example below shows the output offset computation equation
for the non-inverting configuration using the typical bias cur-
rent and offset specifications for A_V = + 2:
Output Offset : V_O = (±I_BN · R_IN ± V_IO) (1 + R_F/R_G) ± I_BI · R_F
Where R_IN is the equivalent input impedance on the non-in-
verting input.
Example computation for A_V = +2, R_F = 237Ω, R_IN = 25Ω:
V_O = (±6μA · 25Ω ± 1mV) (1 + 237/237) ± 8μA · 237 =
±4.20mV
A good design, however, should include a worst case calcu-
lation using Min/Max numbers in the data sheet tables, in
order to ensure "worst case" operation.
Further improvement in the output offset voltage and drift is
possible using the composite amplifiers described in Appli-
cation Note OA-7. The two input bias currents are physically
unrelated in both magnitude and polarity for the current feed-
back topology. It is not possible, therefore, to cancel their
effects by matching the source impedance for the two inputs
(as is commonly done for matched input bias current devices).
The total output noise is computed in a similar fashion to the
output offset voltage. Using the input noise voltage and the
two input noise currents, the output noise is developed
through the same gain equations for each term but combined
as the square root of the sum of squared contributing ele-
ments. See Application Note OA-12 for a full discussion of
noise calculations for current feedback amplifiers.
PRINTED CIRCUIT LAYOUT
Generally, a good high frequency layout will keep power sup-
ply and ground traces away from the inverting input and
output pins. Parasitic capacitances on these nodes to ground
will cause frequency response peaking and possible circuit
oscillations (see Application Note OA-15 for more informa-
tion). National Semiconductor suggests the following evalua-
tion boards as a guide for high frequency layout and as an aid
in device testing and characterization:
These free evaluation boards are shipped when a device
sample request is placed with National Semiconductor.
9
www.national.com