LMC6081 Datasheet, PDF (10/21 Pages) National Semiconductor (TI) – Precision CMOS Single Operational Amplifier

LMC6081
SNOS649C – AUGUST 2000 – REVISED MARCH 2013
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When high input impedances are demanded, guarding of the LMC6081 is suggested. Guarding input lines will
not only reduce leakage, but lowers stray input capacitance as well. (See Printed-Circuit-Board Layout for High
Impedance Work).
The effect of input capacitance can be compensated for by adding a capacitor, C_f, around the feedback resistors
(as in Figure 24 ) such that:
(1)
or
R₁ C_IN ≤ R₂ C_f
(2)
Since it is often difficult to know the exact value of C_IN, C_f can be experimentally adjusted so that the desired
pulse response is achieved. Refer to the LMC660 and LMC662 for a more detailed discussion on compensating
for input capacitance.
Figure 24. Cancelling the Effect of Input Capacitance
CAPACITIVE LOAD TOLERANCE
All rail-to-rail output swing operational amplifiers have voltage gain in the output stage. A compensation capacitor
is normally included in this integrator stage. The frequency location of the dominant pole is affected by the
resistive load on the amplifier. Capacitive load driving capability can be optimized by using an appropriate
resistive load in parallel with the capacitive load (see typical curves).
Direct capacitive loading will reduce the phase margin of many op-amps. A pole in the feedback loop is created
by the combination of the op-amp's output impedance and the capacitive load. This pole induces phase lag at the
unity-gain crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse response.
With a few external components, op amps can easily indirectly drive capacitive loads, as shown in Figure 25.
Figure 25. LMC6081 Noninverting Gain of 10 Amplifier, Compensated to Handle Capacitive Loads
In the circuit of Figure 25, R1 and C1 serve to counteract the loss of phase margin by feeding the high frequency
component of the output signal back to the amplifier's inverting input, thereby preserving phase margin in the
overall feedback loop.
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