DS92LV010A_13 Datasheet, PDF (10/17 Pages) Texas Instruments – Bus LVDS 3.3/5.0V Single Transceiver

DS92LV010A
SNLS007E – MAY 1998 – REVISED APRIL 2013
APPLICATION INFORMATION
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There are a few common practices which should be implied when designing PCB for BLVDS signaling.
Recommended practices are:
• Use at least 4 layer PCB board (BLVDS signals, ground, power and TTL signals).
• Keep drivers and receivers as close to the (BLVDS port side) connector as possible.
• Bypass each BLVDS device and also use distributed bulk capacitance. Surface mount capacitors placed
close to power and ground pins work best. Two or three multi-layer ceramic (MLC) surface mount capacitors
(0.1 µF, and 0.01 µF in parallel should be used between each V_CC and ground. The capacitors should be as
close as possible to the V_CC pin.
• Use the termination resistor which best matches the differential impedance of your transmission line.
• Leave unused LVDS receiver inputs open (floating)
Table 1. Functional Table
MODE SELECTED
DRIVER MODE
RECEIVER MODE
TRI-STATE MODE
LOOP BACK MODE
DE
RE
H
H
L
L
L
H
H
L
Table 2. Transmitter Mode⁽¹⁾
INPUTS
DE
DI
H
L
H
H
H
2 > & > 0.8
L
X
DO+
L
H
X
Z
OUTPUTS
(1) L = Low state
H = High state
RE
L
L
L
H
(1) X = High or Low logic state
Z = High impedance state
L = Low state
H = High state
Table 3. Receiver Mode⁽¹⁾
INPUTS
(RI+)-(RI−)
L (< −100 mV)
H (> +100 mV)
100 mV > & > −100 mV
X
DO−
H
L
X
Z
OUTPUT
L
H
X
Z
Pin Name
DIN
DO±/RI±
R_OUT
RE
DE
GND
V_CC
Pin No.
2
6, 7
3
5
1
4
8
Table 4. Device Pin Descriptions
Input/Output
I
I/O
O
I
I
NA
NA
Description
TTL Driver Input
LVDS Driver Outputs/LVDS Receiver Inputs
TTL Receiver Output
Receiver Enable TTL Input (Active Low)
Driver Enable TTL Input (Active High)
Ground
Power Supply
10
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