DS90C3201_15 Datasheet, PDF (10/22 Pages) Texas Instruments – 3.3V 8 MHz to 135 MHz Dual FPD-Link Transmitter

DS90C3201
SNLS192D – APRIL 2005 – REVISED APRIL 2013
AC Timing Diagrams (continued)
Register addr 26d/1ah[2:0]=[000]
Default
V_DD/2
V_DD/2
RFB=0
RFB=1
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Register addr 26d/1ah[2:0]=[111]
Increases Setup # 800 ps
V_DD/2
Register addr 26d/1ah[2:0]=[110]
Increases Setup # 600 ps
V_DD/2
Register addr 26d/1ah[2:0]=[101]
Increases Setup # 400 ps
Register addr 26d/1ah[2:0]=[100]
Increases Setup # 200 ps
Register addr 26d/1ah[2:0]=[001]
Increases Hold # 400 ps
Register addr 26d/1ah[2:0]=[010]
Increases Hold # 800 ps
Register addr 26d/1ah[2:0]=[011]
Increases Hold # 1200 ps
V_DD/2
V_DD/2
V_DD/2
CLK_IDS # 400 ps
V_DD/2
CLK_IDS # 800 ps
V_DD/2
CLK_IDS # 1200 ps
V_DD/2
CLK_IDS # 800 ps
V_DD/2
CLK_IDS # 600 ps
V_DD/2
CLK_IDS # 400 ps
V_DD/2
CLK_IDS # 200 ps
V_DD/2
V_DD/2
V_DD/2
Figure 14. User Programmable Internal Clock Delay Adjustment for Input Data Setup/Hold Optimization
Input Data Sampling Clock (TCLK_IDS)
10
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