DRV8848_16 Datasheet, PDF (10/27 Pages) Texas Instruments – Dual H-Bridge Motor Driver

DRV8848
SLLSEL7A – OCTOBER 2014 – REVISED NOVEMBER 2015
Feature Description (continued)
OCP
xIN1
xIN2
PWM
VREF
Internal
reference
Pre-
drive
OCP
-
A=6.6
+
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VM
VM
xOUT1
xOUT2
Step
Motor
xISEN
Optional
Figure 6. PWM Motor Driver Circuitry
7.3.2 Bridge Control
Table 1 shows the logic for the inputs xIN1 and xIN2.
xIN1
0
0
1
1
xIN2
0
1
0
1
Table 1. Bridge Control
xOUT1
Z
L
H
L
xOUT2
Z
H
L
L
Function (DC Motor)
Coast (fast decay)
Reverse
Forward
Brake (slow decay)
SPACE
NOTE
Pins AIN1 and AIN2 are tri-level, so when they are left Hi-Z, they are not internally pulled
to logic low. When AIN1 or AIN2 are set to Hi-Z and not in parallel mode, the output driver
maintains the previous state.
10
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