ADS8681_16 Datasheet, PDF (10/74 Pages) Texas Instruments – 16-Bit, High-Speed, Single-Supply, SAR ADC Data Acquisition System with Programmable, Bipolar Input Ranges

ADS8681, ADS8685, ADS8689
SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016
www.ti.com
6.6 Timing Requirements: Conversion Cycle
all minimum and maximum specifications are at T_A = –40°C to +125°C; typical specifications are at T_A = 25°C; AVDD = 5 V,
DVDD = 3.3 V, V_REF = 4.096 V (internal), and maximum throughput (unless otherwise noted)
MIN
TYP
MAX UNIT
TIMING REQUIREMENTS
ADS8681
1000
f_cycle
Sampling frequency
ADS8685
ADS8689
500 kSPS
100
t_cycle
ADC cycle time period
ADS8681
1/f_cycle
335
t_acq
Acquisition time
ADS8685
1000
ns
ADS8689
5000
TIMING SPECIFICATIONS
ADS8681
665
t_conv
Conversion time
ADS8685
ADS8689
1000 ns
5000
6.7 Timing Requirements: Asynchronous Reset
all minimum and maximum specifications are at T_A = –40°C to +125°C; typical specifications are at T_A = 25°C; AVDD = 5 V,
DVDD = 3.3 V, V_REF = 4.096 V (internal), and maximum throughput (unless otherwise noted)
MIN
TYP
MAX UNIT
TIMING REQUIREMENTS
t_{wl_RST}
Pulse duration: RST high
TIMING SPECIFICATIONS
100
ns
t_{D_RST_POR}
t_{D_RST_APP}
t_{NAP_WKUP}
t_PWRUP
Delay time for POR reset: RST rising to RVS rising
Delay time for application reset: RST rising to CONVST/CS rising
Wake-up time: NAP mode
Power-up time: PD mode
20
ms
1
µs
20
µs
20
ms
6.8 Timing Requirements: SPI-Compatible Serial Interface
all minimum and maximum specifications are at T_A = –40°C to +125°C; typical specifications are at T_A = 25°C; AVDD = 5 V,
DVDD = 3.3 V, V_REF = 4.096 V (internal), and maximum throughput (unless otherwise noted)
MIN
TYP
MAX UNIT
TIMING REQUIREMENTS
f_CLK
Serial clock frequency
t_CLK
Serial clock time period
t_{PH_CK}
SCLK high time
t_{PL_CK}
SCLK low time
t_{SU_CSCK}
Setup time: CONVST/CS falling to first SCLK capture edge
t_{SU_CKDI}
Setup time: SDI data valid to SCLK capture edge
t_{HT_CKDI}
Hold time: SCLK capture edge to (previous) data valid on SDI
t_{HT_CKCS}
Delay time: last SCLK capture edge to CONVST/CS rising
TIMING SPECIFICATIONS
1/f_CLK
0.45
0.45
7.5
7.5
7.5
7.5
66.67 MHz
0.55
t_CLK
0.55
t_CLK
ns
ns
ns
ns
t_{DEN_CSDO}
t_{DZ_CSDO}
t_{D_CKDO}
t_{D_CSRVS}
Delay time: CONVST/CS falling edge to data enable
Delay time: CONVST/CS rising to SDO-x going to 3-state
Delay time: SCLK launch edge to (next) data valid on SDO-x
Delay time: CONVST/CS rising edge to RVS falling
9.5
ns
10
ns
12
ns
14
ns
10
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