TPS7H3301-SP Datasheet, PDF (1/30 Pages) Texas Instruments – Sink/Source TID and SEE Hardened 3-A DDR Termination Regulator

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TPS7H3301-SP
SLVSCJ5 – DECEMBER 2015
TPS7H3301-SP Sink/Source TID and SEE Hardened 3-A DDR Termination Regulator With
Built-in VREF
1 Features
•1 QML Class V Qualified to 5962-14228⁽¹⁾⁽²⁾
– Total Ionizing Dose (TID) 100 krad (Si)
– HDR (50-100 rad(Si)/s)
– LDR (.01 rad(Si)/s)
– Single Event Latch-up (SEL), Single Event
Gate Rupture (SEGR), Single Event Burn Out
(SEB) Immune to LET = 65 MeV-cm²/mg
– SET, SEFI, SEU Immune to 65 MeV-cm²/mg
(See Radiation Report for Details)
• Supports DDR, DDR2, DDR3, DDR3LP, and
DDR4 Termination Applications and is Compliant
to JEDEC Standards
• Input Voltage: Supports a 2.5-V and 3.3-V Rail⁽³⁾
• Separate Low Voltage Input (VLDOIN) Down to
.9 V for Improved Power Efficiency⁽³⁾
• 3-A Sink/Source Termination Regulator Includes
Droop Compensation
• Enable Input and Power-Good Output for Power
Supply Sequencing
• VTT Termination Regulator
– Output Voltage Range: 0.5 to 1.75 V
– 3-A Sink and Source Current
– ±20-mV Accuracy
• Integrated Precision Voltage Divider Network With
Sense Input
• Remote Sensing (VOSNS)
• VTTREF Buffered Reference
– VDDQ/2 ±1% Accuracy
– ±10-mA Sink/Source Current
• Built-In Soft Start (SS), Undervoltage Lockout
(UVLO), and Overcurrent Limit (OCL)
Functionality Integrated
2 Applications
• Single Board Computers, Solid-State Recorders,
and Payload Applications where DDR, DDR2,
DDR3, and Low-Power DDR3 and DDR4 Memory
are Used
• Ultra-Fast Transient Power Applications
• Available in Military (–55°C to 125°C)
Temperature Range
• Engineering Evaluation (/EM) Components are
Available⁽⁴⁾
3 Description
The TPS7H3301-SP is a TID and SEE radiation
hardened double data rate (DDR) 3-A termination
regulator with built in VREF. The regulator is
specifically design to provide a complete, compact,
low noise solution for Space DDR termination
applications such as single board computers, solid
state recorders, and payload processing.
The TPS7H3301-SP supports and is compliant to
DDR, DDR2, DDR3, DDR4, and associated low-
power JEDEC specifications. The fast transient
response of the TPS7H3301-SP VTT regulator allows
for a very stable supply during read/write conditions.
The TPS7H3301-SP also includes a built-in VREF
supply that tracks VTT to further reduce the solution
size. During transients, the fast tracking feature of the
VREF supply minimizes any voltage offset between
VTT and VREF. See Description (continued).
Device Information⁽¹⁾⁽²⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS7H3301-SP
CFP (16)
9.60 mm × 11.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Radiation hardness assured (RHA) qualification to 100 krad in
progress; contact factory for details.
(3) Applicable to DDR2, DDR3, DDR3L and DDR4. For DDR,
input voltage = 3.3 V nominal. V_IN is 2.95 to 3.5 V for DDR1
and
V_LDOIN
>
V_TT
for
all
DDRs.
For DDR2 3-A load condition, Vin is 2.45 to 3.5 V.
Vin headroom: V_{in_min} ≥ V_TT + 1.5 V
(4) These units are intended for engineering evaluation only.
They are processed to a noncompliant flow (that is, no burn-
in, and so forth) and are tested to a temperature rating of
25°C only. These units are not suitable for qualification,
production, radiation testing or flight use. Parts are not
warranted for performance over the full MIL specified
temperature range of –55°C to 125°C or operating life.
AGND
VDDQ
DDR ± 2.5 V
DDR2 ± 1.8 V
DDR3 ± 1.5 V
DDR3L ± 1.35 V
DDR4 ± 1.2 V
Standard DDR Application
VTTREF = VDDQSNS / 2
TPS7H3301
1 VTTREF
VTTSNS 16
2 VDDQ
SNS
3 VLDOIN
AGND ¹⁵
VTT/Vo ₁₄
4 VLDOIN
5 VLDOIN
6 PGND
7 ^PGND
8 PGND
VTT/Vo 13
VTT/Vo 12
PGOOD 11 ^{POWER GOOD}
VDD/ ₁₀
Vin
3.3-V or 2.5-V
Supply
EN 9
ENABLE
VTT / Vo = VDDQ / 2
PGND
AGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.