TMS464409 Datasheet, PDF (1/33 Pages) Texas Instruments – 16 777 216 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES

TMS464409, TMS464409P, TMS465409, TMS465409P
16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
D Organization . . . 16777216 by 4 Bits
D Single 3.3-V Power Supply
(± 0.3-V Tolerance)
D Performance Ranges:
ACCESS ACCESS ACCESS EDO
TIME TIME TIME CYCLE
tRAC tCAC tAA tHPC
(MAX) (MAX) (MAX) (MIN)
’46x409/P-40 40 ns 11 ns 20 ns 16 ns
’46x409/P-50 50 ns 13 ns 25 ns 20 ns
’46x409/P-60 60 ns 15 ns 30 ns 25 ns
D Extended-Data-Out (EDO) Operation
D CAS-Before-RAS (CBR) Refresh
D Long Refresh Period (See Available
Options Table)
D Low-Power, Self-Refresh Version
(TMS46x409P)
D 3-State Unlatched Output
D All Inputs / Outputs and Clocks Are
Low-Voltage TTL (LVTTL) Compatible
D High-Reliability Plastic 32-Lead
400-Mil-Wide Thin Small-Outline (TSOP)
Package (DGC Suffix)
D Operating Free-Air Temperature Range
0°C to 70°C
DEVICE
AVAILABLE OPTIONS
SELF-REFRESH
BATTERY
BACKUP
RAS-ONLY
REFRESH
CYCLES
CBR
REFRESH
CYCLES
DGC PACKAGE
( TOP VIEW )
V_{CC 1}
DQ1 ₂
DQ2 3
NC 4
NC 5
NC 6
NC 7
W8
RAS 9
A0 10
A1 11
A2 12
A3 ¹³
A4 ¹⁴
A5 ¹⁵
V_CC ¹⁶
32 ^V_SS
31 ^DQ4
30 DQ3
29 NC
28 NC
27 NC
26 CAS
25 OE
24 A12^†
23 A11
22 A10
21 A9
20 _A8
19 _A7
18 _A6
17 _VSS
† _{A12 is NC for TMS465409 and TMS465409P.}
PIN NOMENCLATURE
A0 – A12
CAS
DQ1 – DQ4
NC
OE
RAS
W
VCC
VSS
Address Inputs
Column-Address Strobe
Data In / Data Out
No Internal Connection
Output Enable
Row-Address Strobe
Write Enable
3.3-V Supply
Ground
TMS464409
—
8 192 in 64 ms 4 096 in 64 ms
TMS464409P
YES
8 192 in 128 ms 4 096 in 128 ms
TMS465409
—
4 096 in 64 ms 4 096 in 64 ms
TMS465409P
YES
4 096 in 128 ms 4 096 in 128 ms
description
The TMS464409 and TMS465409 series are low-voltage, 67 108 864-bit dynamic random-access memories
(DRAMs), organized as 16 777 216 words of 4 bits each. The TMS464409P and TMS465409P series are
high-speed, low-voltage, low-power, self-refresh, 67 108 864-bit DRAMs, organized as 16 777 216 words of
4 bits each. Both sets of devices employ state-of-the-art technology for high performance, reliability, and low
power.
These devices feature maximum RAS access times of 40, 50, and 60 ns. All inputs and outputs, including clocks,
are compatible with LVTTL. All addresses and data-in lines are latched on chip to simplify system design. Data
out is unlatched to allow greater system flexibility.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Copyright © 1997, Texas Instruments Incorporated
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