TMS320DM335_15 Datasheet, PDF (1/160 Pages) Texas Instruments – Digital Media System-on-Chip (DMSoC)

TMS320DM335
www.ti.com
SPRS528C – JULY 2008 – REVISED JUNE 2010
TMS320DM335
Digital Media System-on-Chip (DMSoC)
Check for Samples: TMS320DM335
1 Digital Media System-on-Chip (DMSoC)
1.1 TMS320DM335 Features
123
• Highlights
– High-Performance Digital Media
System-On-Chip (DMSoC)
– Up to 216-MHz ARM926EJ-S™ Clock Rate
– Digital HDTV (720p/1080i) output for
connection to external encoder
– Video Processing Subsystem
• Hardware IPIPE for Real-Time Image
Processing
• Up to 14-bit CCD/CMOS Digital Interface
• Histogram Module
• Resize Image 1/16x to 8x
• Hardware On-Screen Display
• Up to 75-MHz Pixel Clock
• Composite NTSC/PAL video encoder
output
– Peripherals include DDR and mDDR SDRAM,
2 MMC/SD/SDIO and SmartMedia Flash Card
Interfaces, USB 2.0, 3 UARTs and 3 SPIs
– Enhanced Direct-Memory-Access (EDMA)
– Configurable Power-Saving Modes
– On-Chip ARM ROM Bootloader (RBL) to Boot
From NAND Flash, MMC/SD, or UART
– 3.3-V and 1.8-V I/O, 1.3-V Core
– Debug Interface Support
– Up to 104 General-Purpose I/O (GPIO) Pins
– 337-Pin Ball Grid Array at 65 nm Process
Technology
• High-Performance Digital Media
System-on-Chip (DMSoC)
– 135-, 216-MHz ARM926EJ-S™ Clock Rate
– Fully Software-Compatible With ARM™
– Extended Temperature 135- and 216-MHz
Devices are Available
• ARM926EJ-S Core
– Support for 32-Bit and 16-Bit (Thumb Mode)
Instruction Sets
– DSP Instruction Extensions and Single Cycle
MAC
– ARM® Jazelle® Technology
– EmbeddedICE-RT™ Logic for Real-Time
Debug
• ARM9 Memory Architecture
– 16K-Byte Instruction Cache
– 8K-Byte Data Cache
– 32K-Byte RAM
– 8K-Byte ROM
– Little Endian
• Video Processing Subsystem
– Front End Provides:
• Hardware IPIPE for Real-Time Image
Processing
• Up to 14-bit CCD/CMOS Digital Interface
• 16-/8-bit Generic YcBcR-4:2 Interface
(BT.601)
• 10-/8-bit CCIR6565/BT655 Interface
• Up to 75-MHz Pixel Clock
• Histogram Module
• Resize Engine
– Resize Images From 1/16x to 8x
– Separate Horizontal/Vertical Control
– Two Simultaneous Output Paths
– Back End Provides:
• Hardware On-Screen Display (OSD)
• Composite NTSC/PAL video encoder
output
• 8-/16-bit YCC and Up to 18-Bit RGB666
Digital Output
• BT.601/BT.656 Digital YCbCr 4:2:2
(8-/16-Bit) Interface
• Digital HDTV (720p/1080i) output for
connection to external encoder
• External Memory Interfaces (EMIFs)
– DDR2 and mDDR SDRAM 16-bit wide EMIF
With 256 MByte Address Space (1.8-V I/O)
– Asynchronous16-/8-bit Wide EMIF (AEMIF)
• Flash Memory Interfaces
– NAND (8-/16-bit Wide Data)
– OneNAND(16-bit Wide Data)
• Flash Card Interfaces
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Windows is a trademark of Microsoft.
2
All other trademarks are the property of their respective owners.
3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2010, Texas Instruments Incorporated