TMS28F400BZB Datasheet, PDF (1/29 Pages) Texas Instruments – BOOT-BLOCK FLASH MEMORIES

D Organization . . . 524 288 by 8 Bits
262 144 by 16 Bits
D Array-Blocking Architecture
− Two 8K-Byte Parameter Blocks
− One 96K-Byte Main Block
− Three 128K-Byte Main Blocks
− One 16K-Byte Protected Boot Block
− Top or Bottom Boot Locations
D All Inputs / Outputs TTL Compatible
D Maximum Access/Minimum Cycle Time
V_CC ± 10%
’28F400BZx80 80 ns
’28F400BZx90 90 ns
(x = top (T) or bottom (B) boot-block
configuration ordered)
D 10 000 Program/Erase-Cycles
D Two Temperature Ranges
− Commercial . . . 0°C to 70°C
− Extended . . . − 40°C to 85°C
D Low Power Dissipation ( V_CC = 5.5 V )
− Active Write . . . 330 mW ( Byte Write)
− Active Read . . . 330 mW ( Byte Read)
− Active Write . . . 358 mW ( Word Write)
− Active Read . . . 330 mW ( Word Read)
− Block Erase . . . 165 mW
− Standby . . . 0.55 mW (CMOS-Input
Levels)
− Deep Power-Down Mode . . . 0.0066 mW
D Fully Automated On-Chip Erase and
Word / Byte-Program Operations
D Write Protection for Boot Block
D Industry Standard Command State Machine
(CSM)
− Erase Suspend/Resume
− Algorithm-Selection Identifier
TMS28F400BZT, TMS28F400BZB
524288 BY 8ĆBIT/262144 BY 16ĆBIT
BOOTĆBLOCK FLASH MEMORIES
SMJS400E − JUNE 1994 − REVISED JANUARY 1998
DBJ PACKAGE
( TOP VIEW )
V_PP 1
NC 2
A17 3
A7 4
A6 5
A5 6
A4 7
A3 8
A2 9
A1 10
A0 11
E 12
V_SS 13
G 14
DQ0 15
DQ8 16
DQ1 17
DQ9 18
DQ2 19
DQ10 20
DQ3 21
DQ11 22
44 RP
43 W
42 A8
41 A9
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
34 A16
33 BYTE
32 V_SS
31 DQ15/A _−1
30 DQ7
29 DQ14
28 DQ6
27 DQ13
26 DQ5
25 DQ12
24 DQ4
23 V_CC
PIN NOMENCLATURE
A0 −A17
BYTE
DQ0 −DQ14
DQ15/A _−1
E
G
NC
RP
VCC
VPP
VSS
W
Address Inputs
Byte Enable
Data In / Out
Data In / Out (word-wide mode),
Low-Order Address (byte-wide mode)
Chip Enable
Output Enable
No Internal Connection
Reset / Deep Power Down
5-V Power Supply
12-V Power Supply for
Program / Erase
Ground
Write Enable
description
The TMS28F400BZx is a 524 288 by 8-bit / 262 144 by 16-bit (4 194 304-bit), boot-block flash memory that can
be electrically block-erased and reprogrammed. The TMS28F400BZx is organized in a blocked architecture
consisting of one 16K-byte protected boot block, two 8K-byte parameter blocks, one 96K-byte main block, and
three 128K-byte main blocks. The device can be ordered with either a top or bottom boot-block configuration.
Operation as a 512K-byte (8-bit) or a 256K-word (16-bit) organization is user-definable.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1998, Texas Instruments Incorporated
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