SN75LVDS84_08 Datasheet, PDF (1/17 Pages) Texas Instruments – FLATLINK TRANSMITTERS

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SN75LVDS84
SLLS270D – MARCH 1997 – REVISED NOVEMBER 2007
FLATLINK™ TRANSMITTERS
FEATURES
1
•23 21:3 Data Channel Compression at up to 163
Million Bytes per Second Throughput
• Suited for SVGA, XGA, or SXGA Data
Transmission From Controller to Display With
Very Low EMI
• 21 Data Channels Plus Clock-In Low-Voltage
TTL and 3 Data Channels Plus Clock-Out
Low-Voltage Differential
• Operates From a Single 3.3-V Supply and
250 mW (Typ)
• 5-V Tolerant Data Inputs
• ESD Protection Exceeds 6 kV
• SN75LVDS84 Has Falling-Clock
Edge-Triggered Inputs
• Packaged in Thin Shrink Small-Outline
Package (TSSOP) With 20-Mil Terminal Pitch
• Consumes Less Than 1 mW When Disabled
• Wide Phase-Lock Input Frequency Range:
– 31 MHz to 68 MHz
• No External Components Required for PLL
• Outputs Meet or Exceed the Requirements of
ANSI EIA/TIA-644 Standard
• Improved Replacement for the DS90C561
DGG PACKAGE
(TOP VIEW)
D4
1
48
V_CC
2
47
D5
3
46
D6
4
45
GND
5
44
D7
6
43
D8
7
42
V_CC
8
41
D9
9
40
D10
10
39
GND
11
38
D11
12
37
D12
13
36
NC
14
35
D13
15
34
D14
16
33
GND
17
32
D15
18
31
D16
19
30
D17
20
29
V_CC
21
28
D18
22
27
D19
23
26
GND
24
25
NC - Not Connected
D3
D2
GND
D1
D0
NC
LVDSGND
Y0M
Y0P
Y1M
Y1P
LVDSV_CC
LVDSGND
Y2M
Y2P
CLKOUTM
CLKOUTP
LVDSGND
PLLGND
PLLV_CC
PLLGND
SHTDN
CLKIN
D20
P0052-02
DESCRIPTION
The SN75LVDS84 FlatLink™ transmitter contains three 7-bit parallel-load serial-out shift registers, a 7× clock
synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These
functions allow 21 bits of single-ended low-voltage TTL (LVTTL) data to be synchronously transmitted over three
balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 or SN75LVDS86.
When transmitting, data bits D0–D20 are each loaded into registers of the SN75LVDS84 on the falling edge of
the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times and then used to unload the
data registers in 7-bit slices and serially. The three serial streams and a phase-locked clock (CLKOUT) are then
output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
AVAILABLE OPTIONS⁽¹⁾
LATCHING CLOCK EDGE
FALLING
SN75LVDS84DGG
SN75LVDS84DGGR
(1) The R suffix indicates taped and reeled packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a trademark of Texas Instruments.
2
All other trademarks are the property of their respective owners.
3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1997–2007, Texas Instruments Incorporated