SN74LVTH273-EP Datasheet, PDF (1/9 Pages) Texas Instruments – 3.3-V ABT OCTAL D-TYPE FLIP-FLOP WITH CLEAR

D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree^†
D Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V V_CC )
D Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
D Supports Unregulated Battery Operation
Down to 2.7 V
D Buffered Clock and Direct-Clear Inputs
D Individual Data Input to Each Flip-Flop
D I_off Supports Partial Power-Down-Mode
Operation
† _{Component qualification in accordance with JEDEC and industry}
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
SN74LVTH273ĆEP
3.3ĆV ABT OCTAL DĆTYPE FLIPĆFLOP
WITH CLEAR
SCBS769A − NOVEMBER 2003 − REVISED JUNE 2006
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Latch-Up Performance Exceeds 500 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
PW OR NS PACKAGE
(TOP VIEW)
CLR 1
1Q 2
1D 3
2D 4
2Q 5
3Q 6
3D 7
4D 8
4Q ⁹
GND ¹⁰
20 V_CC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 _5Q
11 _CLK
description/ordering information
This octal D-type flip-flop is designed specifically for low-voltage (3.3 V) V_CC operation, but with the capability
to provide a TTL interface to a 5-V system environment.
The SN74LVTH273 is a positive-edge-triggered flip-flop with a direct clear (CLR) input. Information at the data
(D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of
the clock pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition
time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal
has no effect at the output.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
This device is fully specified for partial power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 85°C TSSOP − PW Tape and reel
SN74LVTH273IPWREP LH273EP
−55°C to 125°C SOP − NS
Tape and reel
SN74LVTH273MNSREP LVTH273EP
‡ _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are}
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright  2006, Texas Instruments Incorporated
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