SN74LVC373A-EP Datasheet, PDF (1/14 Pages) Texas Instruments – OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

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FEATURES
• Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
• Extended Temperature Performance of –40°C
to 125°C and –55°C to 125°C
• Enhanced Diminishing Manufacturing Sources
(DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree ⁽¹⁾
• ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
• Operates From 2 V to 3.6 V
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 7.5 ns at 3.3 V
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
SN74LVC373A-EP
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS737C – NOVEMBER 2003 – REVISED MARCH 2007
• Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
• Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With 3.3-V
V_CC)
• I_off Supports Partial-Power-Down Mode
Operation
DB, DW OR PW PACKAGE
(TOP VIEW)
OE 1
1Q 2
1D 3
2D 4
2Q 5
3Q 6
3D 7
4D 8
4Q 9
GND 10
20 V_CC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 LE
DESCRIPTION/ORDERING INFORMATION
The SN74LVC373A octal transparent D-type latch is designed for 2.7-V to 3.6-V V_CC operation.
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q
outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN74LVC373A is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION⁽¹⁾
T_A
–40°C to 125°C
–55°C to 125°C
PACKAGE ⁽²⁾
SOIC – DW
Reel of 2000
TSSOP – PW
Reel of 2000
SSOP – DB
Reel of 2000
ORDERABLE PART NUMBER
SN74LVC373AQDWREP
SN74LVC373AQPWREP
SN74LVC373AMDBREP
TOP-SIDE MARKING
C373AEP
C373AEP
C373AEP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2007, Texas Instruments Incorporated