SN74LVC16373_14 Datasheet, PDF (1/12 Pages) Texas Instruments – 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

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FEATURES
• Member of the Texas Instruments Widebus™
Family
• EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
• Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
> 2 V at V_CC = 3.3 V, T_A = 25°C
• Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
• Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
• Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
DESCRIPTION
This 16-bit transparent D-type latch is designed for
2.7-V to 3.6-V V_CC operation.
The SN74LVC16373 is particularly suitable for
implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers. It can be used as
two 8-bit latches or one 16-bit latch. When the
latch-enable (LE) input is high, the Q outputs follow
the data (D) inputs. When LE is taken low, the Q
outputs are latched at the levels set up at the D
inputs.
SN74LVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS315B – NOVEMBER 1993 – REVISED MARCH 2005
DGG OR DL PACKAGE
(TOP VIEW)
1OE 1
1Q1 2
1Q2 ³
GND 4
1Q3 5
1Q4 6
V_CC 7
1Q5 ⁸
1Q6 ⁹
GND ¹⁰
1Q7 11
1Q8 12
2Q1 13
2Q2 ¹⁴
GND ¹⁵
2Q3 ¹⁶
2Q4 ¹⁷
V_CC 18
2Q5 ¹⁹
2Q6 ²⁰
GND ²¹
2Q7 ²²
2Q8 ²³
2OE ²⁴
48 1LE
47 1D1
46 _1D2
45 GND
44 1D3
43 1D4
42 V_CC
41 _1D5
40 _1D6
39 _GND
38 1D7
37 1D8
36 2D1
35 _2D2
34 _GND
33 _2D3
32 _2D4
31 V_CC
30 _2D5
29 _2D6
28 _GND
27 _2D7
26 _2D8
25 _2LE
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74LVC16373 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1993–2005, Texas Instruments Incorporated