SN74LV595A-EP Datasheet, PDF (1/17 Pages) Texas Instruments – 8-BIT SHIFT REGISTER WITH 3-STATE OUTPUT REGISTERS

D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree^†
D 2-V to 5.5-V V_CC Operation
D Max t_pd of 7.4 ns at 5 V
D Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
D Typical V_OHV (Output V_OH Undershoot)
>2.3 V at V_CC = 3.3 V, T_A = 25°C
† _{Component qualification in accordance with JEDEC and industry}
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
SN74LV595AĆEP
8ĆBIT SHIFT REGISTER
WITH 3ĆSTATE OUTPUT REGISTERS
SCLS568B − JANUARY 2004 − REVISED MAY 2004
D Supports Mixed-Mode Voltage Operation on
All Ports
D 8-Bit Serial-In, Parallel-Out Shift
D I_off Supports Partial-Power-Down Mode
Operation
D Shift Register Has Direct Clear
PW PACKAGE
(TOP VIEW)
Q_{B 1}
Q_C 2
Q_D 3
Q_E 4
Q_F 5
Q_G 6
Q_H 7
GND 8
16 ^V_CC
15 Q_A
14 SER
13 OE
12 RCLK
11 SRCLK
10 SRCLR
9 Q_H′
description/ordering information
The SN74LV595A is an 8-bit shift register designed for 2-V to 5.5-V V_CC operation.
This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The
storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register.
The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output for
cascading. When the output-enable (OE) input is high, all outputs except Q_H′ are in the high-impedance state.
Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both
clocks are connected together, the shift register always is one clock pulse ahead of the storage register.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 85°C
TSSOP − PW Reel of 2000 SN74LV595AIPWREP LV595EP
‡ _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines}
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright  2004, Texas Instruments Incorporated
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