SN74ALVCH162836_09 Datasheet, PDF (1/16 Pages) Texas Instruments – 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

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FEATURES
• Member of the Texas Instruments Widebus™
Family
• EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
• Output Port Has Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
• Designed to Comply With JEDEC 168-Pin and
200-Pin SDRAM Buffered DIMM Specification
• ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
• Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink Small-Outline
(DGG), and Thin Very Small-Outline (DGV)
Packages
NOTE: For tape-and-reel order entry, the DGGR package is
abbreviated to GR, and the DGVR package is abbreviated
to VR.
DESCRIPTION
This 20-bit universal bus driver is designed for 1.65-V
to 3.6-V V_CC operation.
Data flow from A to Y is controlled by the
output-enable (OE) input. The device operates in the
transparent mode when the latch-enable (LE) input is
low. When LE is high, the A data is latched if the
clock (CLK) input is held at a high or low logic level. If
LE is high, the A data is stored in the latch/flip-flop on
the low-to-high transition of CLK. When OE is high,
the outputs are in the high-impedance state.
SN74ALVCH162836
20-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES122F – JULY 1997 – REVISED OCTOBER 2004
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
OE 1
Y1 2
Y2 3
GND 4
Y3 5
Y4 6
V_CC 7
Y5 8
Y6 9
Y7 10
GND 11
Y8 12
Y9 13
Y10 14
Y11 15
Y12 16
Y13 17
GND 18
Y14 19
Y15 20
Y16 21
V_CC 22
Y17 23
Y18 24
GND 25
Y19 26
Y20 27
NC 28
56 CLK
55 A1
54 A2
53 GND
52 A3
51 A4
50 V_CC
49 A5
48 A6
47 A7
46 GND
45 A8
44 A9
43 A10
42 A11
41 A12
40 A13
39 GND
38 A14
37 A15
36 A16
35 V_CC
34 A17
33 A18
32 GND
31 A19
30 A20
29 LE
NC − No internal connection
The output port includes equivalent 26-Ω series resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162836 is characterized for operation from -40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1997–2004, Texas Instruments Incorporated