SMJ320C50KGDC Datasheet, PDF (1/7 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE

D Processed to MIL-PRF-38535
D Fast Instruction Cycle Time of 30 ns and
40 ns
D Source-Code Compatible With all ’C1x and
’C2x Devices
D RAM-Based Operation
− 9K-Word × 16-Bit Dual-Access On-Chip
Program/ Data RAM
− 1 056-Word × 16-Bit Dual-Access On-Chip
Data RAM
D 2K-Word × 16-Bit On-Chip Boot ROM
D 224K-Word × 16-Bit Maximum Addressable
External Memory Space (64K-Word
Program, 64K-Word Data, 64K-Word I / O,
and 32K-Word Global)
D 32-Bit Arithmetic Logic Unit (ALU)
− 32-Bit Accumulator (ACC)
− 32-Bit Accumulator Buffer (ACCB)
D 16-Bit Parallel Logic Unit (PLU)
SMJ320C50KGD
DIGITAL SIGNAL PROCESSOR
KNOWN GOOD DIE
SGZS007B − JUNE 1996 − REVISED JUNE 2000
D 16 × 16-Bit Multiplier, 32-Bit Product
D Eleven Context Switch Registers
D Two Buffers for Circular Addressing
D Full-Duplex Synchronous Serial Port
D Time-Division Multiplexed (TDM) Serial Port
D Timer With Control and Counter Registers
D Sixteen Software-Programmable Wait-State
Generators
D Divide-By-1 Clock Option
D IEEE Standard 1149.1^† (JTAG) Test-Access
Port
D Operations are Fully Static
D Fabricated Using the Texas Instruments (TI)
Enhanced Performance Implanted CMOS
(EPIC) 0.64-µm Technology
D Military Operating Temperature Range
−55°C to 125°C
description
The SMJ320C50KGD digital signal processor (DSP) is a high-performance, 16-bit, fixed-point processor
manufactured in 0.64-µm double-level metal CMOS technology.
The SMJ320C50 KGD employs the hot-chuck-probe process. This process uses standard probed product that
is tested again, this time at full data sheet specifications, in wafer form at speed and elevated temperature
(125°C). Each individual die is then sawed, inspected, and packaged for shipment.
A number of enhancements to the basic ’C2x architecture give the ’C50 a minimum 2x performance over the
previous generation. A four-deep instruction pipeline, which incorporates delayed branching, delayed call to a
subroutine, and delayed return from a subroutine, allows the ’C50 to perform instructions in fewer cycles. The
addition of a PLU gives the ’C50 a method of manipulating bits in data memory without using the ACC and the
ALU. The ’C50 has additional shifting and scaling capabilities for proper alignment of multiplicands or for storage
of values to data memory.
With the addition of the IDLE2 instruction, the ’C50 achieves low-power consumption. IDLE2 removes the
functional clock from the internal hardware of the ’C50 that puts it into a total-sleep mode using only 5 µA. A
low-logic level on an external interrupt with a chip duration of at least five clock cycles ends the IDLE2 mode.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† _{IEEE Standard 1149.1−1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture}
EPIC is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2000, Texas Instruments Incorporated
On products compliant to MILĆPRFĆ38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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