SM34020A Datasheet, PDF (1/94 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

Not Recommended for New Designs
SM34020A
GRAPHICS SYSTEM PROCESSOR
SGUS057 − FEBRUARY 2005
D Class B High-Reliability Processing
D 1-µm CMOS Technology
D Military Operating Temperature Range
−40°C to 110°C
D SM34020A-32/ 40
125 / 100-ns Instruction Cycle Time
D Fully Programmable 32-Bit
General-Purpose Processor With
512-Megabyte Linear Address Range
(Bit Addressable)
D Second-Generation Graphics System
Processor
− Object-Code Compatible With the
SMJ34010
− Enhanced Instruction Set
− Optimized Graphics Instructions
− Coprocessor Interface
D Pixel Processing, XY Addressing, and
Window Checking Built Into the Instruction
Set
D Programmable 1-, 2-, 4-, 8-, 16-, or 32-Bit
Pixel Size With 16 Boolean and Six
Arithmetic Pixel Processing Options
(Raster Ops)
D 512-Byte LRU On-Chip Instruction Cache
D Optimized DRAM / VRAM Interface
− Page-Mode for Burst Memory Operations
− Dynamic Bus Sizing (16-Bit and
32-Bit Transfers)
− Byte-Oriented CAS Strobes
D Flexible Host Processor Interface
− Supports Host Transfers
− Direct Access to All of the SMJ34020A
Address Space
− Implicit Addressing
− Prefetch for Enhanced Read Access
description
145-PIN GRID ARRAY PACKAGE
( TOP VIEW )
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
132-PIN QUAD FLATPACK
( TOP VIEW )
D Programmable CRT Control
− Composite Sync Mode
− Separate Sync Mode
− Synchronization to External Sync
D Direct Support for Special Features of
1M VRAMs
− Load Write Mask
− Load Color Mask
− Block Write
− Write Using the Write Mask
D Flexible Multi-Processor Interface
D Packaging Options
− 145-Pin Grid Array Ceramic Package
(GB Suffix)
The SM34020A graphics system processor (GSP) is the second generation of an advanced high-performance
CMOS 32-bit microprocessor optimized for graphics display systems. With a built-in instruction cache, the ability
to simultaneously access memory and registers, and an instruction set designed to expedite raster graphics
operations, the SM34020A provides user-programmable control of the CRT interface as well as the memory
interface (both standard DRAM and multiport video RAM). The 4-gigabit (512-megabyte) physical address
space is addressable on bit boundaries using variable width data fields (1 to 32 bits). Additional graphics
addressing modes support 1-, 2-, 4-, 8-, 16- and 32-bit wide pixels.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2004, Texas Instruments Incorporated
On products compliant to MILĆPRFĆ38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
1