LMK0482X Datasheet, PDF (1/114 Pages) Texas Instruments – JEDEC JESD204B Support

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LMK04821, LMK04826, LMK04828
SNAS605AQ – MARCH 2013 – REVISED AUGUST 2014
LMK0482x Ultra Low-Noise JESD204B Compliant
Clock Jitter Cleaner with Dual Loop PLLs
1 Features
•1 JEDEC JESD204B Support
• Ultra-Low RMS Jitter
– 88 fs RMS jitter (12 kHz to 20 MHz)
– 91 fs RMS jitter (100 Hz to 20 MHz)
– –162.5 dBc/Hz Noise Floor at 245.76 MHz
• Up to 14 Differential Device Clocks from PLL2
– Up to 7 SYSREF Clocks
– Maximum Clock Output Frequency 3.1 GHz
– LVPECL, LVDS, HSDS, LCPECL
Programmable Outputs from PLL2
• Up to 1 Buffered VCXO/Crystal Output from PLL1
– LVPECL, LVDS, 2xLVCMOS Programmable
• Dual Loop PLLatinum™ PLL Architecture
• PLL1
– Up to 3 Redundant Input Clocks
– Automatic and Manual Switch-over Modes
– Hitless Switching and LOS
– Integrated Low-Noise Crystal Oscillator Circuit
– Holdover mode when Input Clocks are lost
• PLL2
– Normalized [1 Hz] PLL Noise Floor of
-227 dBc/Hz
– Phase Detector Rate up to 155 MHz
– OSCin Frequency-doubler
– Two Integrated Low-Noise VCOs
• 50% Duty Cycle Output Divides, 1 to 32
(even and odd)
• Precision Digital Delay, Dynamically Adjustable
• 25 ps Step Analog Delay
• Multi-mode: Dual PLL, single PLL, and Clock
Distribution
• Industrial Temperature Range: -40 to 85°C
• 3.15 V to 3.45 V Operation
• Package: 64-pin QFN (9.0 x 9.0 x 0.8 mm)
2 Applications
• Wireless Infrastructure
• Data Converter Clocking
• Networking, SONET/SDH, DSLAM
• Medical / Video / Military / Aerospace
• Test and Measurement
3 Description
The LMK0482x family is the industry's highest
performance clock conditioner with JEDEC
JESD204B support.
The 14 clock outputs from PLL2 can be configured to
drive seven JESD204B converters or other logic
devices using device and SYSREF clocks. SYSREF
can be provided using both DC and AC coupling. Not
limited to JESD204B applications, each of the 14
outputs can be individually configured as high
performance outputs for traditional clocking systems.
The high performance combined with features like the
ability to trade off between power or performance,
dual VCOs, dynamic digital delay, holdover, and
glitchless analog delay make the LMK0482x family
ideal for providing flexible high performance clocking
trees.
Part Number
LMK04821
LMK04826B
LMK04828B
Device Information⁽¹⁾
VCO0 Frequency
VCO1 Frequency
1930 to 2075 MHz
2920 to 3080 MHz
VCO1 Div = ÷2 to ÷8
(÷2 = 1460 to 1540 MHz)
1840 to 1970 MHz 2440 to 2505 MHz
2370 to 2630 MHz 2920 to 3080 MHz
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
Recovered
³GLUW\´FORFNRU
clean clock
Crystal or
VCXO
CLKin0
Backup
Reference
Clock
CLKin1
OSCout
LMK0482xB
DCLKout12
SDCLKout13
DCLKout8 &
DCLKout10
LMX2581
PLL+VCO
FPGA
ADC
DCLKout0 &
DCLKout2
SDCLKout1 &
SDCLKout3
SDCLKout9 &
SDCLKout11
DCLKout4,
SDCLKout5
Serializer/
Deserializer
DDAACC
0XOWLSOH³FOHDQ´
clocks at different
frequencies
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.