CD74HC297 Datasheet, PDF (1/15 Pages) Texas Instruments – High-Speed CMOS Logic Digital Phase-Locked-Loop

Data sheet acquired from Harris Semiconductor
SCHS177B
November 1997 - Revised May 2003
CD54HC297, CD74HC297,
CD74HCT297
High-Speed CMOS Logic
Digital Phase-Locked Loop
[ /Title
(CD74
HC297
,
CD74
HCT29
7)
/Sub-
ject
(High-
Speed
CMOS
Logic
Digi-
tal
Phase-
Locked
Features
Description
• Digital Design Avoids Analog Compensation Errors
• Easily Cascadable for Higher Order Loops
• Useful Frequency Range
- K-Clock . . . . . . . . . . . . . . . . . . . . . . . . . .DC to 55MHz (Typ)
- I/D-Clock . . . . . . . . . . . . . . . . . . . . DC to 35MHz (Typ)
• Dynamically Variable Bandwidth
• Very Narrow Bandwidth Attainable
• Power-On Reset
• Output Capability
- Standard . . . . . . . . . . . . . . . . . . . . XORPD_OUT, ECPD_OUT
- Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/D_OUT
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• ’HC297 Types
- Operation Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 to 6V
- High Noise Immunity N_IL = 30%, N_IH = 30% of V_CC at 5V
• CD74HCT297 Types
- Operation Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.5 to 5.5V
- Direct LSTTL Input Logic Compatibility
V_IL = 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility I_I ≤ 1µA at V_OL, V_OH
Pinout
CD54HC297
(CERDIP)
CD74HC297, CD74HCT29
(PDIP)
TOP VIEW
B1
A2
EN_CTR 3
K_CP 4
I/D_CP 5
D/U 6
I/D_OUT 7
GND 8
16 V_CC
15 C
14 D
13 φA₂
12 ECPD_OUT
11 XORPD_OUT
10 φB
9 φA₁
The ’HC297 and CD74HCT297 are high-speed silicon gate
CMOS devices that are pin-compatible with low power Schot-
tky TTL (LSTTL).
These devices are designed to provide a simple, cost-effec-
tive solution to high-accuracy, digital, phase-locked-loop appli-
cations. They contain all the necessary circuits, with the
exception of the divide-by-N counter, to build first-order
phase-locked-loops.
Both EXCLUSIVE-OR (XORPD) and edge-controlled phase
detectors (ECPD) are provided for maximum flexibility. The
input signals for the EXCLUSIVE-OR phase detector must
have a 50% duty factor to obtain the maximum lock-range.
Proper partitioning of the loop function, with many of the build-
ing blocks external to the package, makes it easy for the
designer to incorporate ripple cancellation (see Figure 2) or to
cascade to higher order phase-locked-loops.
The length of the up/down K-counter is digitally programmable
according to the K-counter function table. With A, B, C and D
all LOW, the K-counter is disabled. With A HIGH and B, C and
D LOW, the K-counter is only three stages long, which widens
the bandwidth or capture range and shortens the lock time of
the loop. When A, B, C and D are all programmed HIGH, the
K-counter becomes seventeen stages long, which narrows
the bandwidth or capture range and lengthens the lock time.
Real-time control of loop bandwidth by manipulating the A to
D inputs can maximize the overall performance of the digital
phase-locked-loop.
The ’HC297 and CD74HCT297 can perform the classic first
order phase-locked-loop function without using analog com-
ponents. The accuracy of the digital phase-locked-loop
(DPLL) is not affected by V_CC and temperature variations but
depends solely on accuracies of the K-clock and loop propa-
gation delays.
Ordering Information
PART NUMBER
CD54HC297F3A
CD74HC297E
CD74HCT297E
TEMP. RANGE (^oC)
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld PDIP
16 Ld PDIP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
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