CD74FCT652 Datasheet, PDF (1/12 Pages) Texas Instruments – BiCMOS OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS

CD74FCT652
BiCMOS OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCBS734A – JULY 2000 – REVISED JULY 2000
D BiCMOS Technology With Low Quiescent
Power
D Buffered Inputs
D Noninverted Outputs
D Input/Output Isolation From V_CC
D Controlled Output Edge Rates
D 64-mA Output Sink Current
D Output Voltage Swing Limited to 3.7 V
D SCR Latch-Up-Resistant BiCMOS Process
and Circuit Design
D Multiplexed Real-Time and Stored Data
D Package Options Include Plastic
Small-Outline (M) Package and Standard
Plastic (EN) DIP
EN OR M PACKAGE
(TOP VIEW)
CLKAB ₁
SAB ₂
OEAB ₃
A1 4
A2 5
A3 6
A4 7
A5 8
A6 9
A7 10
A8 11
GND 12
24 ^V_CC
23 ^CLKBA
22 ^SBA
21 OEBA
20 B1
19 B2
18 B3
17 B4
16 B5
15 B6
14 B7
13 B8
description
The CD74FCT652 is an octal bus transceiver and resistor with 3-state outputs. It consists of D-type flip-flops
and control circuitry, arranged for multiplexed transmission of data directly from the data bus or from the internal
storage registers. Output-enable (OEAB and OEBA) inputs control the transceiver functions. The select-control
(SAB and SBA) inputs select real-time-data or stored-data transfer. A low-input level selects real-time data, and
a high-input level selects stored data. The select-control circuitry eliminates the typical decoding glitch that
occurs in a multiplexer during the transition between stored data and real-time data.
The device uses a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS
transistors that limits the output high level to two diode drops below V_CC. This resultant lowering of output swing
(0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes V_CC
bounce and ground bounce and their effects during simultaneous output switching. The output configuration
also enhances switching speed and is capable of sinking 64 mA.
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flop by low-to-high transitions at
the appropriate clock terminal (CLKAB and CLKBA), regardless of the state of the select or enable control
terminals. When SAB and SBA are in the real-time-transfer mode, it also is possible to store data without using
the internal D-type flip-flop by simultaneously enabling OEAB and OEBA. In this configuration, each output
reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each
set of bus lines remains at its last state.
To ensure the high-impedance state during power up or power down, OEBA should be tied to V_CC through a
pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
(B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the driver (A to B).
The CD74FCT652 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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