CD74FCT651 Datasheet, PDF (1/11 Pages) Texas Instruments – BiCMOS FCT Interface Logic, Octal Bus Transceivers/Registers, Three-State

CD74FCT651,
CD74FCT652
Data sheet acquired from Harris Semiconductor
SCHS262
BiCMOS FCT Interface Logic, Octal Bus
January 1997
Features
• Buffered Inputs
NOFO_U^T_sRRe ^E_CNCMEO^OW_S^MD_T^M_e^E_c^E_h^SN_n^I_o^GD_lo^NE_g^SD_y
•
Typical Propagation Delay:
T_A = 25^oC, C_L = 50pF
6.8ns
at
V_CC
=
5V,
Transceivers/Registers, Three-State
Description
The CD74FCT651 and CD74FCT652 three-state, octal bus
transceivers/registers use a small geometry BiCMOS technol-
ogy. The output stage is a combination of bipolar and CMOS
transistors that limits the output HIGH level to two diode drops
• CD75FCT651
- Inverting
• CD74FCT652
below V_CC. This resultant lowering of output swing (0V to
3.7V) reduces power bus ringing (a source of EMI) and mini-
mizes V_CC bounce and ground bounce and their effects dur-
ing simultaneous output switching. The output configuration
- Noninverting
also enhances switching speed and is capable of sinking 64
milliamperes.
• Family Features
- SCR Latchup Resistant BiCMOS Process and
Circuit Design
These devices consist of bus transceiver circuits, D-Type flip-
flops, and control circuitry arranged for multiplexed transmis-
sion of data directly from the data bus or from the internal stor-
- Speed of Bipolar FAST™/AS/S
age registers. Output Enables OEAB and OEBA are provided
- 64mA Output Sink Current
- Output Voltage Swing Limited to 3.7V at V_CC = 5V
to control the transceiver functions. SAB and SBA control pins
are provided to select whether real-time or stored data is
transferred. The circuitry used for select control will eliminate
- Controlled Output Edge Rates
the typical decoding glitch that occurs in a multiplexer during
- Input/Output Isolation to V_CC
- BiCMOS Technology with Low Quiescent Power
the transition between stored and real-time data. A LOW input
level selects real-time data and a HIGH selects stored data.
The following examples demonstrate the four fundamental
Ordering Information
bus management functions that can be performed with the
octal bus transceivers and registers.
PART NUMBER
CD74FCT651EN
TEMP.
RANGE (^oC) PACKAGE
0 to 70 24 Ld PDIP
PKG.
NO.
E24.3
Data on the A or B data bus, or both, can be stored in the inter-
nal D flip-flops by low to high transitions at the appropriate clock
pins (CAB or CBA) regardless of the select or enable control
CD74FCT652EN
0 to 70 24 Ld PDIP E24.3
pins. When SAB and SBA are in the real-time transfer mode, it
CD74FCT651M
CD74FCT652M
0 to 70
0 to 70
24 Ld SOIC
24 Ld SOIC
M24.3
M24.3
is also possible to store data without using the internal D-Type
flip-flops by simultaneously enabling OEAB and OEBA. In this
configuration, each output reinforces its input. Thus, when all
NOTE: When ordering the suffix M packages, use the entire part
other data sources to the two sets of bus lines are at high
number. Add the suffix 96 to obtain the variant in the tape and reel. _{impedance, each set of bus lines will remain at its last state.}
Pinouts
CD74FCT651 (PDIP, SOIC)
TOP VIEW
CAB 1
SAB 2
OEAB 3
A0 4
A1 5
A2 6
A3 7
A4 8
A5 9
A6 10
A7 11
GND 12
24 VCC
23 CBA
22 SBA
21 OEBA
20 B0
19 B1
18 B2
17 B3
16 B4
15 B5
14 B6
13 B7
CD74FCT652 (PDIP, SOIC)
TOP VIEW
CAB 1
SAB 2
OEAB 3
A0 4
A1 5
A2 6
A3 7
A4 8
A5 9
A6 10
A7 11
GND 12
24 VCC
23 CBA
22 SBA
21 OEBA
20 B0
19 B1
18 B2
17 B3
16 B4
15 B5
14 B6
13 B7
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a trademark of Fairchild Semiconductor.
Copyright © Harris Corporation 1997
8-1
File Number 2394.2