CD74FCT373_16 Datasheet, PDF (1/12 Pages) Texas Instruments – BiCMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

CD74FCT373
BiCMOS OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCBS738 – JULY 2000
D BiCMOS Technology With Low Quiescent
Power
D Buffered Inputs
D Noninverted Outputs
D Input/Output Isolation From V_CC
D 48-mA Output Sink Current
D Controlled Output Edge Rates
D Output Voltage Swing Limited to 3.7 V
D SCR Latch-Up-Resistant BiCMOS Process
and Circuit Design
D Package Options Include Plastic
Small-Outline (M) and Shrink Small-Outline
(SM) Packages and Standard Plastic (E) DIP
E, M, OR SM PACKAGE
(TOP VIEW)
OE 1
1Q 2
1D 3
2D 4
2Q 5
3Q 6
3D 7
4D 8
4Q 9
GND 10
20 V_CC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 LE
description
The CD74FCT373 is an octal, transparent, D-type latch with 3-state outputs using a small-geometry BiCMOS
technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level
to two diode drops below V_CC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing
[a source of electromagnetic interference (EMI)] and minimizes V_CC bounce and ground bounce and their
effects during simultaneous output switching. The output configuration also enhances switching speed and is
capable of sinking 48 mA.
The outputs are transparent to the inputs when latch enable (LE) is high. When LE is high, the Q outputs follow
the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. The latch
operation is independent of output-enable (OE) input.
OE can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state.
When OE is high, the outputs are in the high-impedance state. In the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to
drive bus lines without interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The CD74FCT373 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each latch)
INPUTS
OE LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 2000, Texas Instruments Incorporated
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