ADS5292_13 Datasheet, PDF (1/67 Pages) Texas Instruments – Octal Channel 12-Bit, 80 MSPS and Low-Power ADC

www.ti.com
ADS5292
SLAS788B – NOVEMBER 2011 – REVISED JULY 2012
Octal Channel 12-Bit, 80 MSPS and Low-Power ADC
Check for Samples: ADS5292
FEATURES
1
• Maximum Sample Rate: 80 MSPS/12-Bit
• High Signal-to-Noise Ratio
– 70-dBFS SNR at 5 MHz/80 MSPS
– 71.5-dBFS SNR at 5 MHz/80 MSPS and
Decimation Filter = 2
– 85-dBc SFDR at 5 MHz/80 MSPS
• Low Power Consumption
– 48 mW/CH at 50 MSPS
– 54 mW/CH at 65 MSPS
– 66 mW/CH at 80 MSPS (2 LVDS Wire Per
Channel)
• Digital Processing Block
– Programmable FIR Decimation Filter and
Oversampling to Minimize Harmonic
Interference
– Programmable IIR High Pass Filter to
Minimize DC Offset
– Programmable Digital Gain: 0 dB to 12 dB
– 2- or 4- Channel Averaging
• Flexible Serialized LVDS Outputs:
– One or Two wires of LVDS Output Lines per
Channel Depending on ADC Sampling Rate
– Programmable Mapping Between ADC
Input Channels and LVDS Output Pins-
Eases Board Design
– Variety of Test Patterns to Verify Data
Capture by FPGA/Receiver
• Internal and External References
• 1.8V Operation for Low Power Consumption
• Low-Frequency Noise Suppression
• Recovery From 6-dB Overload within 1 Clock
Cycle
• Package: 12-mm × 12-mm 80-Pin QFP
APPLICATIONS
• Ultrasound Imaging
• Communication Applications
• Multi-channel Data Acquisition
DESCRIPTION
Using CMOS process technology and innovative
circuit techniques, the ADS5292 is a low power
80MSPS 8-Channel ADC. Low power consumption,
high SNR, low SFDR, and consistent overload
recovery allow users to design high performance
systems.
The ADS5292 has a digital processing block that
integrates several commonly used digital functions for
improving system performance. It includes a digital
filter module that has built-in decimation filters (with
low-pass, high-pass and band-pass characteristics).
The decimation rate is also programmable (by 2, by
4, or by 8). This makes it useful for narrow-band
applications, where the filters can be used
conveniently to improve SNR and knock-off
harmonics, while at the same time reducing the
output data rate. The device includes an averaging
mode where two channels (or even four channels)
can be averaged to improve SNR.
Serial LVDS outputs reduce the number of interface
lines and enable the highest system integration. The
digital data from each channel ADC can be output
over one or two wires of LVDS output lines
depending on the ADC sampling rate. This 2-wire
interface helps keep the serial data rate low, allowing
low cost FPGA based receivers to be used even at
high sample rate. A unique feature is the
programmable mapping module that allows flexible
mapping between the input channels and the LVDS
output pins. This helps greatly reduce the complexity
of LVDS output routing and can potentially result in
cheaper system boards by reducing the number of
PCB layers.
The device integrates an internal reference trimmed
to accurately match across devices. Best
performance is expected to be achieved through the
internal reference mode. The device can be driven
with external references as well.
The device is available in a 12 mm × 12 mm 80-pin
QFP. It is specified over a –40°C to 85°C operating
temperature range. ADS5292 is completely pin-to-pin
and register compatible to ADS5294.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated