74AC11379_10 Datasheet, PDF (1/7 Pages) Texas Instruments – QUAD D- TYPE FLIP FLOP WITH DATA ENABLE

• Contains Four Flip-Flops with Double-Rail
Outputs
• Clock Enable Latched to Avoid False
Clocking
• Applications Include: Buffer/Storage
Registers, Shift Registers, Pattern
Generators
• Flow-Through Architecture Optimizes PCB
Layout
• Center-Pin V_CC and GND Pin
Configurations Minimize High-Speed
Switching Noise
• EPIC  (Enhanced-Performance Implanted
CMOS) 1-µm Process
• 500-mA Typical Latch-Up Immunity at
125°C
• Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
74AC11379
QUAD D-TYPE FLIP-FLOP
WITH CLOCK ENABLE
SCAS104 − MARCH 1990 − REVISED APRIL 1993
DW OR N PACKAGE
(TOP VIEW)
1Q ₁
2Q 2
2Q 3
GND 4
GND 5
GND 6
GND 7
3Q ⁸
3Q ⁹
4Q ¹⁰
20 ^1Q
19 CLKEN
18 1D
17 2D
16 V_CC
15 V_CC
14 3D
13 _4D
12 _CLK
11 _4Q
description
These circuits are positive-edge-triggered D-type flip-flops with a clock-enable input.
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the
positive-going edge of the clock pulse if the clock-enable input (CLKEN) is low. Clock triggering occurs at a
particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock
input is at either the high or low level, the data (D) input signal has no effect at the output. The circuits are
designed to prevent false clocking by transitions at the clock-enable (CLKEN) input.
The 74AC11379 is characterized for operation from − 40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUTS
CLKEN CLK D
Q
Q
H
X
X
Q0 Q0
L
↑
H
H
L
L
↑
L
L
H
X
L
X
Q0 Q0
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright  1993, Texas Instruments Incorporated
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