TMS320DM6446_07 Datasheet, PDF (99/231 Pages) Texas Instruments – Digital Media System-on-Chip

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TMS320DM6446
Digital Media System-on-Chip
SPRS283E – DECEMBER 2005 – REVISED MARCH 2007
Warm reset is activated by driving the RESET pin active low, while TRST is inactive high. This does not
reset test or ARM emulation logic. An ARM emulator session will stay alive during warm reset, but a
C64x+ emulator session will not.
Maximum reset is initiated by the emulator or the watchdog timer and the reset effects are the same as a
warm reset. The emulator initiates a maximum reset via the ICEPICK module. When the watchdog timer
counter reaches zero, this will initiate a maximum reset to recover from a runaway condition. Both of the
maximum reset initiators can be masked by the ARM emulator.
System reset is initiated by the emulator and is a soft reset. Memory contents are maintained. Test,
emulation, clock, and power control logic are unaffected. The emulator initiates a system reset via the
C64x+ emulation logic, or through ICECRUSHER. Both of these reset initiators are non-maskable resets.
The C64x+ DSP has an internal reset input that allows a host to control it. This reset is configured through
a MMR bit (MDCTL[39].LRSTz) in the PSC module. When in C64x+ local reset, the slave DMA port on
C64x+ will remain active and the internal memory will be accessible, including access to the VICP memory
through the L2 port (UMAP port).
For details on reset control/status registers, see the TMS320DM644x DMSoC ARM Subsystem Reference
Guide (literature number SPRUE14)
For information on peripheral selection at the rising edge of RESET, see the Device Configuration section
of this data manual.
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Peripheral and Electrical Specifications
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