TMS320DM6446_07 Datasheet, PDF (21/231 Pages) Texas Instruments – Digital Media System-on-Chip

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START
ADDRESS
0x01C4 2034
0x01C4 2400
0x01C4 8000
0x01C4 8400
0x01C6 0000
0x01C6 4000
0x01C6 6000
0x01C6 6800
0x01C6 7000
0x01C6 7800
0x01C6 8000
0x01C7 0000
0x01C7 4000
0x01C8 0000
0x01C8 1000
0x01C8 2000
0x01C8 4000
0x01C8 4800
0x01C8 5000
0x01CC 0000
0x01CE 0000
0x01D0 0000
0x01E0 0000
0x01E0 1000
0x01E0 2000
0x01E0 4000
0x01E1 0000
0x01E2 0000
0x01E4 0000
0x0200 0000
0x0400 0000
0x0600 0000
0x0800 0000
0x0A00 0000
0x0C00 0000
TMS320DM6446
Digital Media System-on-Chip
SPRS283E – DECEMBER 2005 – REVISED MARCH 2007
Table 2-4. Configuration Memory Map Summary (continued)
END
ADDRESS
0x01C4 23FF
0x01C4 7FFF
0x01C4 83FF
0x01C5 FFFF
0x01C6 3FFF
0x01C6 5FFF
0x01C6 67FF
0x01C6 6FFF
0x01C6 77FF
0x01C6 7FFF
0x01C6 FFFF
0x01C7 3FFF
0x01C7 FFFF
0x01C8 0FFF
0x01C8 1FFF
0x01C8 3FFF
0x01C8 47FF
0x01C8 4FFF
0x01CB FFFF
0x01CD FFFF
0x01CF FFFF
0x01DF FFFF
0x01E0 0FFF
0x01E0 1FFF
0x01E0 3FFF
0x01E0 FFFF
0x01E1 FFFF
0x01E3 FFFF
0x01FF FFFF
0x03FF FFFF
0x05FF FFFF
0x07FF FFFF
0x09FF FFFF
0x0BFF FFFF
0x0FFF FFFF
SIZE
(Bytes)
1K - 52
23K
1K
95K
16K
8K
2K
2K
2K
2K
32K
16K
48K
4K
4K
8K
2K
2K
236K
128K
128K
1M
4K
4K
8K
48K
64K
128K
1792K
32M
32M
32M
32M
32M
64M
ARM/EDMA
Reserved
ARM Interrupt Controller
Reserved
USB2.0 Registers / RAM
ATA/CF
SPI
GPIO
HPI
Reserved
VPSS Registers
Reserved
EMAC Control Registers
EMAC Control Module Registers
EMAC Control Module RAM
MDIO Control Registers
Reserved
VICP
Reserved
EMIFA Control
VLYNQ Control Registers
ASP
Reserved
MMC/SD/SDIO
Reserved
EMIFA Data/Code (CS2)
EMIFA Data/Code (CS3)
EMIFA Data/Code (CS4)
EMIFA Data/Code (CS5)
Reserved
VLYNQ (Remote)
C64x+
Reserved
HPI
Reserved
VICP
Reserved
ASP
Reserved
EMIFA Data (CS2)
EMIFA Data (CS3)
EMIFA Data (CS4)
EMIFA Data (CS5)
Reserved
2.6 Pin Assignments
Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in
the smallest possible package. Pin multiplexing is controlled using a combination of hardware
configuration at device reset and software programmable register settings. For more information on pin
muxing, see Section 3.5.2, Multiplexed Pin Configurations, of this document.
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Device Overview
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