TMS320C6712 Datasheet, PDF (99/110 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSORS

TMS320C6712, TMS320C6712C, TMS320C6712D
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS148J − AUGUST 2000 − REVISED MAY 2004
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 11b, CLKXP = 0^†‡ (see Figure 47) [C6712C/C6712D]
NO.
PARAMETER
12C−150
MASTER^§
SLAVE
MIN MAX
MIN
MAX
12D−150
MASTER^§
SLAVE
MIN MAX
MIN
MAX
UNIT
1
t_h(CKXL-FXL)
Hold time, FSX low
after CLKX low^¶
L−2 L+3
L−2 L+3
ns
2
t_d(FXL-CKXH)
Delay time, FSX low
to CLKX high^#
T−2 T+3
T−2 T+3
ns
3
t_d(CKXL-DXV)
Delay time, CLKX low
to DX valid
−3
4 6P + 2 10P + 17
−3
4 6P + 2 10P + 17 ns
Disable time, DX high
6
t_{dis(CKXL-DXHZ)}
impedance following
last data bit from
−4
CLKX low
4 6P + 1.5 10P + 17
−2
4 6P + 3 10P + 17 ns
7
t_d(FXL-DXV)
Delay time, FSX low
to DX valid
H−2 H+4
4P + 2 8P + 17 H − 2 H + 6.5
4P + 2 8P + 17 ns
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.}
‡ _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
§ _{S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)}
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶ _{FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX}
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# _{FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock}
(CLKX).
CLKX
FSX
DX
DR
1
6
Bit 0
Bit 0
2
7
3
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 47. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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