TSC2117 Datasheet, PDF (97/192 Pages) Texas Instruments – Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller

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TSC2117
Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D
Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller
SLAS550A – APRIL 2009 – REVISED JUNE 2009
5.9.1.4 DSP Mode
The audio interface of the TSC2117 can be put into DSP mode by programming page 0/register 27, D(7:6)
= 01. In DSP mode, the falling edge of the word clock starts the data transfer with the left channel data
first and immediately followed by the right channel data. Each data bit is valid on the falling edge of the bit
clock.
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
BIT
CLOCK
DATA
NNN
---
1 23
NN N
3210- - -
123
3210
LD(n)
RD(n)
LD(n) = n'th sample of left channel data
RD(n) = n'th sample of right channel data
Figure 5-69. Timing Diagram for DSP Mode
NNN
---
3
1 23
LD (n+1)
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
BIT
CLOCK
DATA
NNN
---
123
N NN
3210- - -
12 3
321 0
LD(n)
RD(n)
LD(n) = n'th sample of left channel data
RD(n) = n'th sample of right channel data
Figure 5-70. Timing Diagram for DSP Mode With Offset = 1
NNN
---
123
LD(n+1)
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
BIT
CLOCK
DATA
NNN
---
123
N NN
3210- - -
12 3
321 0
LD(n)
RD(n)
NNN
---
3
123
LD (n+1)
Figure 5-71. Timing Diagram for DSP Mode With Offset = 0 and Bit Clock Inverted
For DSP mode, the number of bit-clocks per frame should be greater than or equal to twice the
programmed word-length of the data. Also the programmed offset value should be less than the number of
bit-clocks per frame by at least the programmed word-length of the data.
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APPLICATION INFORMATION
97