LM3S9790 Datasheet, PDF (967/1185 Pages) Texas Instruments – Stellaris® LM3S9790 Microcontroller

Stellaris® LM3S9790 Microcontroller
OTG A /
Host
Register 145: USB Control and Status Endpoint 0 Low (USBCSRL0), offset
0x102
USBCSRL0 is an 8-bit register that provides control and status bits for endpoint 0.
OTG B /
Device
OTG A / Host Mode
USB Control and Status Endpoint 0 Low (USBCSRL0)
Base 0x4005.0000
Offset 0x102
Type W1C, reset 0x00
7
6
5
4
3
2
1
0
NAKTO STATUS REQPKT ERROR SETUP STALLED TXRDY RXRDY
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit/Field
7
6
5
Name
NAKTO
STATUS
REQPKT
Type
R/W
R/W
R/W
Reset
0
0
0
Description
NAK Timeout
Value Description
0 No timeout.
1 Indicates that endpoint 0 is halted following the receipt of NAK
responses for longer than the time set by the USBNAKLMT
register.
Software must clear this bit to allow the endpoint to continue.
STATUS Packet
Value Description
0 No transaction.
1 Initiates a STATUS stage transaction. This bit must be set at
the same time as the TXRDY or REQPKT bit is set.
Setting this bit ensures that the DT bit is set in the USBCSRH0 register
so that a DATA1 packet is used for the STATUS stage transaction.
This bit is automatically cleared when the STATUS stage is over.
Request Packet
Value Description
0 No request.
1 Requests an IN transaction.
This bit is cleared when the RXRDY bit is set.
June 14, 2010
967
Texas Instruments-Advance Information