LM3S9790 Datasheet, PDF (474/1185 Pages) Texas Instruments – Stellaris® LM3S9790 Microcontroller

General-Purpose Timers
Register 3: GPTM Timer B Mode (GPTMTBMR), offset 0x008
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TBAMS bit, clear the TBCMR bit, and configure the TBMR field to
0x2.
In 16-bit timer configuration, these bits control the 16-bit timer modes for Timer B. In 32-bit timer
configuration, this register’s contents are ignored, and GPTMTAMR is used.
GPTM Timer B Mode (GPTMTBMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
TBSNAPS TBWOT TBMIE TBCDIR TBAMS TBCMR
TBMR
Type RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:8
7
Name
reserved
TBSNAPS
Type
RO
R/W
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
GPTM Timer B Snap-Shot Mode
Value Description
0 Snap-shot mode is disabled.
1 If Timer B is configured in the periodic mode, the actual
free-running value of Timer B is loaded at the time-out event
into the GPTM Timer B (GPTMTBR) register.
6
TBWOT
R/W
0
GPTM Timer B Wait-on-Trigger
Value Description
0 Timer B begins counting as soon as it is enabled.
1 If Timer B is enabled (TBEN is set in the GPTMCTL register),
Timer B does not begin counting until it receives an it receives
a trigger from the timer in the previous position in the daisy
chain. See Figure 12-5 on page 465. This function is valid for
both one-shot and periodic modes.
474
June 14, 2010
Texas Instruments-Advance Information