XIO3130_10 Datasheet, PDF (92/142 Pages) Texas Instruments – Data Manual

XIO3130
SLLS693F – MAY 2007 – REVISED JANUARY 2010
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4.3.11 Primary Bus Number
This register specifies the bus number of the PCI bus segment for the downstream port primary interface
(i.e., the internal PCI bus).
PCI register offset:
Register type:
18h
Read/Write
Default value:
00h
BIT NUMBER
RESET STATE
76543210
00000000
4.3.12 Secondary Bus Number
This register specifies the bus number of the PCI bus segment for the downstream port secondary
interface (i.e., the PCI Express interface). The XIO3130 uses this register to determine how to respond to
a Type 1 configuration transaction.
PCI register offset: 19h
Register type:
Default value:
Read/Write
00h
BIT NUMBER
RESET STATE
76543210
00000000
4.3.13 Subordinate Bus Number
This register specifies the bus number of the highest number PCI bus segment that is downstream of the
XIO3130 downstream port. The XIO3130 uses this register to determine how to respond to a Type 1
configuration transaction.
PCI register offset:
Register type:
Default value:
1Ah
Read/Write
00h
BIT NUMBER
RESET STATE
76543210
00000000
4.3.14 Secondary Latency Timer Register
This register does not apply to PCI-Express, so it is hardwired to zero.
PCI register offset:
Register type:
1Bh
Read only
Default value:
00h
BIT NUMBER
RESET STATE
76543210
00000000
92
XIO3130 Configuration Register Space
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