XIO3130_10 Datasheet, PDF (106/142 Pages) Texas Instruments – Data Manual

XIO3130
SLLS693F – MAY 2007 – REVISED JANUARY 2010
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4.3.43 Next-Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the
XIO3130 downstream port. This register reads 90h, which points to the PCI Express Capabilities registers.
PCI register offset:
Register type:
81h
Read only
Default value:
90h
BIT NUMBER
RESET STATE
76543210
10010000
4.3.44 Subsystem Vendor ID Register
This register is used for system and option card identification and may be required for certain operating
systems. This read-only register is a direct reflection of the upstream port’s Subsystem Access register,
which is read/write and is initialized through the EEPROM (if present).
PCI register offset: 84h
Register type:
Default value:
Read only
0000h
BIT NUMBER
RESET STATE
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4.3.45 Subsystem ID Register
This register is used for system and option card identification and may be required for certain operating
systems. This read-only register is a direct reflection of the upstream port’s Subsystem Access register,
which is read/write and is initialized through the EEPROM (if present).
PCI register offset:
Register type:
Default value:
86h
Read only
0000h
BIT NUMBER
RESET STATE
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4.3.46 PCI Express Capability ID Register
This read-only register identifies the linked list item as the register for PCI Express Capabilities. When
read, this register returns 10h.
PCI register offset:
Register type:
90h
Read only
Default value:
10h
BIT NUMBER
RESET STATE
76543210
00010000
106 XIO3130 Configuration Register Space
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