VCA8500_0803 Datasheet, PDF (9/40 Pages) Texas Instruments – 8-Channel, Ultralow-Power, Variable Gain Amplifier with Low-Noise Pre-Amp

VCA8500
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BYTE #1
D0:D7
Control
D7
0
BIT #
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7 (MSB)
BIT #
D8 (LSB)
D9
D10
D11
D12
D13
D14
D15 (MSB)
BIT #
D16 (LSB)
D17
D18
D19
D20
D21
D22
D23 (MSB)
SBOS390A – JANUARY 2008 – REVISED MARCH 2008
INPUT REGISTER BIT MAPS
BYTE #2
D8:D11
D12:D15
CH1
CH2
Register Map
BYTE #3
D16:D19 D20:D23
CH3
CH4
BYTE #4
D24:D27 D28:D31
CH5
CH6
BYTE #5
D32:D35 D36:D39
CH7
CH8
Table 2. Default Register Configuration
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
1
1
Table 3. Byte 1—Control Byte Register Map
NAME
1
R/W
PWR
BW
CL
Mode
PG0
PG1
DESCRIPTION
Start bit; must be a ‘1’ (high); 40-bit countdown starts with first falling clock edge.
1 = Write, 0 = Read; read prevents latching of new data/bits. Control register remains
latched with previously loaded data.
1 = Power-down mode enabled (shutdown).
Low-pass filter bandwidth setting (see Table 8)
Clamp level setting (see Table 8)
1 = TGC mode, 0 = CW doppler mode (TGC powered down)
LSB of PGA gain control (see Table 9)
MSB of PGA gain control
NAME
DB1:1
DB1:2
DB1:3
DB1:4
DB2:1
DB2:2
DB2:3
DB2:4
Table 4. Byte 2—First Data Byte
DESCRIPTION
Channel 1, LSB of matrix control
Channel 1, matrix control
Channel 1, matrix control
Channel 1, MSB of matrix control
Channel 2, LSB of matrix control
Channel 2, matrix control
Channel 2, matrix control
Channel 2; MSB of matrix control
NAME
DB3:1
DB3:2
DB3:3
DB3:4
DB4:1
DB4:2
DB4:3
DB4:4
Table 5. Byte 3—Second Data Byte
DESCRIPTION
Channel 3, LSB of matrix control
Channel 3, matrix control
Channel 3, matrix control
Channel 3, MSB of matrix control
Channel 4, LSB of matrix control
Channel 4, matrix control
Channel 4, matrix control
Channel 4, MSB of matrix control
Copyright © 2008, Texas Instruments Incorporated
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