TLV320AIC3263 Datasheet, PDF (9/62 Pages) Texas Instruments – Check for Samples: TLV320AIC3263

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Electrical Characteristics
TLV320AIC3263
SLAS923 – JUNE 2013
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) ⁽¹⁾
AVDD1_18, AVDD2_18, AVDD4_18, AVDD_18 to AVSS1, AVSS2, AVSS4, AVSS respectively⁽²⁾
RECVDD_33 to RECVSS
DVDD to DVSS
IOVDDx to IOVSS
HVDD_18 to AVSS
CPVDD_18 to CPVSS
SVDD to SVSS, SPK_V to SVSS, and MICBIAS_VDD to AVSS3⁽³⁾
Digital Input voltage to ground
Analog input voltage to ground
VBAT
Operating temperature range
Storage temperature range
Junction temperature (T_J Max)
Power dissipation
WCSP-81 (DSBGA)
package (YZF)
θ_JA Junction-to-ambient thermal resistance
θ_JCtop Junction-to-case (top) thermal resistance
θ_JB Junction-to-board thermal resistance
Psi_JT Junction-to-top characterization parameter
Psi_JB Junction-to-board characterization parameter
VALUE
–0.3 to 2.2
–0.3 to 3.9
–0.3 to 2.2
–0.3 to 3.9
–0.3 to 2.2
–0.3 to 2.2
–0.3 to 6.0
IOVSS – 0.3 to IOVDDx +
0.3
AVSS – 0.3 to AVDDx_18
+ 0.3
–0.3 to 6
–40 to 85
–55 to 125
105
(T_J Max – TA)/ θ_JA
39.1
0.1
12.0
0.7
11.5
UNIT
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
W
°C/W
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) It's recommended to keep all AVDDx_18 supplies within ± 50 mV of each other.
(3) It's recommended to keep SVDD and SPK_V supplies within ± 50 mV of each other.
Recommended Operating Conditions
AVDD1_18,
AVDD2_18,
AVDD4_18,
AVDD_18
Power Supply Voltage Range
RECVDD_33
IOVDD1,
IOVDD2,
IOVDD3
DVDD ⁽⁴⁾
Power Supply Voltage Range
CPVDD_18 Power Supply Voltage Range
HVDD_18
Referenced to AVSS1, AVSS2, AVSS4, AVSS
respectively⁽¹⁾ It is recommended to connect each
of these supplies to a single supply rail.
Referenced to RECVSS
Referenced to IOVSS⁽¹⁾
Referenced to DVSS⁽¹⁾
Referenced to CPVSS ⁽¹⁾
Referenced to AVSS⁽¹⁾
Ground-centered
Configuration
Unipolar
Configuration
MIN NOM
1.5 ⁽²⁾
1.8
1.65 ⁽³⁾
3.3
1.1
1.26 1.8
1.26 1.8
1.5 ⁽³⁾
1.8
1.65 ⁽³⁾
MAX UNIT
1.95 V
3.6
3.6
1.95
1.95 V
1.95
1.95
(1) All grounds on board are tied together, so they should not differ in voltage by more than 0.1V max, for any combination of ground
signals. AVDDx_18 are within +/- 0.05 V of each other. SVDD and SPK_V are within +/- 0.05 V of each other.
(2) For optimal performance with CM=0.9V, min AVDD = 1.8V.
(3) Minimum voltage for HVDD_18 should be greater than or equal to AVDD2_18.
(4) At DVDD values lower than 1.65V, the PLL and SAR ADC do not function. Please see table in SLAU475, Maximum TLV320AIC3263
Clock Frequencies for details on maximum clock frequencies.
Copyright © 2013, Texas Instruments Incorporated
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