TLV320AIC3263 Datasheet, PDF (27/62 Pages) Texas Instruments – Check for Samples: TLV320AIC3263

www.ti.com
Typical DSP Timing Characteristics
Specifications are at 25° C with DVDD = 1.8 V.
WCLK
BCLK
DOUT
DIN
t_d(WS)
t_d(WS)
t_d(DO-BCLK)
t_s(DI)
Figure 5. DSP/Mono PCM Timing in Master Mode
TLV320AIC3263
SLAS923 – JUNE 2013
t_h(DI)
t_d (WS)
t_d (DO-BCLK)
t_s(DI)
t_h(DI)
t_r
t_f
Table 4. DSP/Mono PCM Timing in Master Mode (see Figure 5)
PARAMETER
WCLK delay
BCLK to DOUT delay
DIN setup
DIN hold
BCLK Rise time
BCLK Fall time
IOVDDx=1.8V
MIN
MAX
22
22
4
4
10
10
IOVDDx=3.3V
MIN MAX
20
20
4
4
8
8
UNITS
ns
ns
ns
ns
ns
ns
WCLK
BCLK
DOUT
DIN
t_H(BCLK)
t_h(ws)
t_L(BCLK)
t_s(ws)
t_h(ws)
t_d(DO-BCLK)
t_h(ws)
t_s(DI)
Figure 6. DSP/Mono PCM Timing in Slave Mode
t_h(DI)
t_H (BCLK)
t_L (BCLK)
t_s(WS)
t_h(WS)
t_d (DO-BCLK)
t_s(DI)
t_h(DI)
t_r
t_f
Table 5. DSP/Mono PCM Timing in Slave Mode (see Figure 6)
PARAMETER
BCLK high period
BCLK low period
WCLK setup
WCLK hold
BCLK to DOUT delay
DIN setup
DIN hold
BCLK Rise time
BCLK Fall time
IOVDDx=1.8V
MIN MAX
30
30
4
4
22
5
5
5
5
IOVDDx=3.3V
MIN MAX
30
30
4
4
20
5
5
4
4
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TLV320AIC3263
Submit Documentation Feedback
27