TCA6416A Datasheet, PDF (9/32 Pages) Texas Instruments – LOW-VOLTAGE 16-BIT I2C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

TCA6416A
www.ti.com ....................................................................................................................................................................................................... SCPS194 – MAY 2009
Reset Input (RESET)
The RESET input can be asserted to initialize the system while keeping the V_CCP at its operating level. A reset
can be accomplished by holding the RESET pin low for a minimum of t_W. The TCA6416A registers and
I²C/SMBus state machine are changed to their default state once RESET is low (0). When RESET is high (1),
the I/O levels at the P port can be changed externally or through the master. This input requires a pullup resistor
to V_CCI, if no active connection is used.
Interrupt Output (INT)
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time t_iv, the signal
INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or
when data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur
during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this
pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the
state of the pin does not match the contents of the Input Port register.
The INT output has an open-drain structure and requires pullup resistor to V_CCP or V_CCI depending on the
application. INT should be connected to the voltage source of the device that requires the interrupt information.
Bus Transactions
Data is exchanged between the master and TCA6416A through write and read commands.
Writes
Data is transmitted to the TCA6416A by sending the device address and setting the least-significant bit (LSB) to
a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which
register receives the data that follows the command byte. There is no limitation on the number of data bytes sent
in one write transmission.
The eight registers within the TCA6416A are configured to operate as four register pairs. The four pairs are input
ports, output ports, polarity inversion ports and configuration ports. After sending data to one register, the next
data byte is sent to the other register in the pair (see Figure 6 and Figure 7). For example, if the first byte is send
to Output Port 1 (register 3), the next byte is stored in Output Port 0 (register 2).
There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register
may be updated independently of the other registers.
SCL
12 3 456 7 8 9
Slave Address
Command Byte
Data to Port 0
Data to Port 1
SDA
S0
1
0
00
0
AD
DR
0
A0
00
00
0
10
A 0.7
Data 0
Start Condition
Write to Port
R/W Acknowledge
From Slave
Acknowledge
From Slave
0.0 A 1.7
Data 1
Acknowledge
From Slave
1.0 A P
Data Out from Port 0
Data Out from Port 1
t_pv
Figure 6. Write to Output Port Register
Data Valid
t_pv
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